AD9653BCPZ-125 Analog Devices, AD9653BCPZ-125 Datasheet

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AD9653BCPZ-125

Manufacturer Part Number
AD9653BCPZ-125
Description
the ad9653 is a quad, 16-bit, 125 msps analog-to-digital converter (adc) with an...
Manufacturer
Analog Devices
Datasheet

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Part Number:
AD9653BCPZ-125
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Data Sheet
FEATURES
1.8 V supply operation
Low power: 164 mW per channel at 125 MSPS
SNR = 76.5 dBFS at 70 MHz (2.0 V p-p input span)
SNR = 77.5 dBFS at 70 MHz (2.6 V p-p input span)
SFDR = 90 dBc (to Nyquist, 2.0 V p-p input span)
DNL = ±0.7 LSB; INL = ±3.5 LSB (2.0 V p-p input span)
Serial LVDS (ANSI-644, default) and low power, reduced
650 MHz full power analog bandwidth
2 V p-p input voltage range (supports up to 2.6 V p-p)
Serial port control
APPLICATIONS
Medical ultrasound and MRI
High speed imaging
Quadrature radio receivers
Diversity radio receivers
Test equipment
GENERAL DESCRIPTION
The
verter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 125 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled. The ADC contains several features
designed to maximize flexibility and minimize system cost, such
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
range option (similar to IEEE 1596.3)
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Multichip sync and clock divider
Programmable output clock and data alignment
Standby mode
AD9653
is a quad, 16-bit, 125 MSPS analog-to-digital con-
Quad, 16-Bit, 125 MSPS, Serial LVDS 1.8 V
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
as programmable output clock and data alignment and digital
test pattern generation. The available digital test patterns
include built-in deterministic and pseudorandom patterns, along
with custom user-defined test patterns entered via the serial port
interface (SPI).
The
It is specified over the industrial temperature range of −40°C to
+85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
SENSE
RBIAS
VIN+A
VIN–A
VIN+B
VIN–B
AGND
VIN+C
VIN–C
VIN+D
VIN–D
VREF
VCM
AD9653
Analog-to-Digital Converter
Small Footprint.
Four ADCs are contained in a small, space-saving package.
Low power of 164 mW/channel at 125 MSPS with scalable
power options.
Pin compatible to the
12-bit quad ADC.
Ease of Use.
A data clock output (DCO) operates at frequencies of up to
500 MHz and supports double data rate (DDR) operation.
User Flexibility.
The SPI control offers a wide range of flexible features to
meet specific system requirements.
AVDD
SELECT
SERIAL PORT
INTERFACE
REF
FUNCTIONAL BLOCK DIAGRAM
is available in a RoHS-compliant, 48-lead LFCSP.
PIPELINE
PIPELINE
PIPELINE
PIPELINE
ADC
ADC
ADC
ADC
1V
PDWN
©2012 Analog Devices, Inc. All rights reserved.
16
16
16
16
AD9253
SERIALIZER
SERIALIZER
AD9653
SERIALIZER
SERIALIZER
MANAGEMENT
Figure 1.
DIGITAL
DIGITAL
DIGITAL
DIGITAL
CLOCK
14-bit quad and the
DRVDD
SERIAL
SERIAL
SERIAL
SERIAL
SERIAL
SERIAL
SERIAL
SERIAL
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
AD9653
www.analog.com
AD9633
D0+A
D0–A
D1+A
D1–A
D0+B
D0–B
D1+B
D1–B
FCO+
FCO–
D0+C
D0–C
D1+C
D1–C
D0+D
D0–D
D1+D
D1–D
DCO+
DCO–

Related parts for AD9653BCPZ-125

AD9653BCPZ-125 Summary of contents

Page 1

... Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ...

Page 2

AD9653 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications .......................................................................... 5 Digital Specifications ...

Page 3

Data Sheet SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2.0 V p-p full-scale differential input at −1.0 dBFS; V Table 1. 1 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching ...

Page 4

AD9653 AVDD = 1.8 V, DRVDD = 1.8 V, 2.6 V p-p full-scale differential input at −1.0 dBFS; V Table 2. 1 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral ...

Page 5

Data Sheet AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2.0 V p-p full-scale differential input at −1.0 dBFS; V Table 3. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR 9.7 MHz MHz IN f ...

Page 6

AD9653 AVDD = 1.8 V, DRVDD = 1.8 V, 2.6 V p-p full-scale differential input at −1.0 dBFS; V noted. Table 4. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR 9.7 MHz MHz ...

Page 7

Data Sheet DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted. Table 5. 1 Parameter CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage 2 Input Voltage Range Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance ...

Page 8

AD9653 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted. Table Parameter CLOCK 3 Input Clock Rate Conversion Rate Clock Pulse Width High ( Clock Pulse Width Low ( ...

Page 9

Data Sheet TIMING SPECIFICATIONS Table 7. Parameter Description SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK+ setup time SSYNC t SYNC to rising edge of CLK+ hold time HSYNC SPI TIMING REQUIREMENTS See Figure 75 t Setup time ...

Page 10

AD9653 N – 1 VIN± CLK– CLK+ t CPD DCO– DDR DCO+ SDR DCO t FCO FCO– FCO D0–A BITWISE MODE D0+A D1–A D1+A FCO– FCO+ D0–A BYTEWISE MODE D0+A D1–A D1+A N – ...

Page 11

Data Sheet ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Electrical AVDD to AGND DRVDD to AGND Digital Outputs (D0±x, D1±x, DCO+, DCO−, FCO+, FCO−) to AGND CLK+, CLK− to AGND VIN+x, VIN−x to AGND SCLK/DTP, SDIO/OLM, CSB to AGND SYNC, PDWN ...

Page 12

AD9653 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 10. Pin Function Descriptions Pin No. Mnemonic 0 AGND, Exposed Pad 1 VIN+D 2 VIN− 34, 39, 45, 46 AVDD 5, 6 CLK−, CLK DRVDD 9, 10 D1−D, ...

Page 13

Data Sheet Pin No. Mnemonic 44 SYNC 47 VIN−C 48 VIN+C Description Digital Input. SYNC input to clock divider. ADC C Analog Input Complement. ADC C Analog Input True. Rev Page AD9653 ...

Page 14

AD9653 TYPICAL PERFORMANCE CHARACTERISTICS V = 1.0 V REF 0 125MSPS –15 9.7MHz AT –1dBFS SNR = 77.1dB (78.1dBFS) –30 SFDR = 96.8dBc –45 –60 –75 – –105 –120 –135 ...

Page 15

Data Sheet 120 SFDRFS 100 SNRFS 80 60 SFDR 40 20 SNR 0 –20 –100 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 13. SNR/SFDR vs. Input Amplitude (AIN 125 MSPS 1.0 V ...

Page 16

AD9653 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 OUTPUT CODE Figure 19. DNL 9.7 MHz 125 MSPS SAMPLE 160000 140000 120000 100000 80000 60000 40000 20000 0 CODE Figure 20. Input-Referred Noise ...

Page 17

Data Sheet V = 1.3 V REF 0 125MSPS –15 9.7MHz AT –1dBFS SNR = 79.1dB (80.1dBFS) –30 SFDR = 93.5dBc –45 –60 –75 – –105 –120 –135 FREQUENCY (MHz) ...

Page 18

AD9653 0 80MSPS –15 15MHz AT –1dBFS SNR = 79.0dB (80.0dBFS) –30 SFDR = 90.5dBc –45 –60 –75 –90 4 –105 5 6 –120 –135 FREQUENCY (MHz) Figure 30. Single-Tone 16k FFT with ...

Page 19

Data Sheet 94 92 SFDR (dBc SNR (dBFS TEMPERATURE (°C) Figure 36. SNR/SFDR vs. Temperature 125 MSPS 1.3 V SAMPLE REF 4.5 3.0 1.5 0 ...

Page 20

AD9653 100 SFDR (dBc) 80 SNR (dBFS SAMPLE RATE (MSPS) Figure 42. SNR/SFDR vs. Sample Rate MHz, Clock Divider = 100 120 = 1.3 V REF ...

Page 21

Data Sheet EQUIVALENT CIRCUITS AVDD VIN±x Figure 43. Equivalent Analog Input Circuit AVDD 10Ω CLK+ 15kΩ AVDD 15kΩ 10Ω CLK– Figure 44. Equivalent Clock Input Circuit AVDD 400Ω SDIO/OLM 31kΩ Figure 45. Equivalent SDIO/OLM Input Circuit DRVDD V V D0–x, ...

Page 22

AD9653 THEORY OF OPERATION The AD9653 is a multistage, pipelined ADC. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 16-bit result in the ...

Page 23

Data Sheet 110 SFDR (dBc) 100 90 SNRFS (dBFS 0.6 0.7 0.8 0.9 1.0 COMMON-MODE VOLTAGE (V) Figure 53. SNR/SFDR vs. Common-Mode Voltage 9.7 MHz 125 MSPS ...

Page 24

AD9653 0.1µF 2V p-p Figure 56. Differential Double Balun Input Configuration for Baseband Applications 2V p-p If the internal reference of the AD9653 converters to improve gain matching, the loading of the reference by the other converters must be considered. ...

Page 25

Data Sheet –2 –4 –6 –8 –40 – TEMPERATURE (°C) Figure 60. Typical V = 1.0 V Drift REF –5 –10 –15 –40 – TEMPERATURE (°C) Figure 61. Typical V ...

Page 26

AD9653 0.1µF CLOCK INPUT AD951x LVDS DRIVER 0.1µF CLOCK INPUT 50kΩ 50kΩ Figure 65. Differential LVDS Sample Clock ( GHz OPTIONAL 0.1µF 1kΩ AD951x CLOCK CMOS DRIVER INPUT 1kΩ 50Ω 1 50Ω RESISTOR IS OPTIONAL. 1 ...

Page 27

Data Sheet ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), ...

Page 28

AD9653 D0 400mV/DIV D1 400mV/DIV DCO 400mV/DIV FCO 400mV/DIV Figure 72. LVDS Output Timing Example in Reduced Range Mode An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histo- ...

Page 29

Data Sheet Two output clocks are provided to assist in capturing data from the AD9653. The DCO is used to clock the output data and is equal to four times the sample clock (CLK) rate for the default mode of ...

Page 30

AD9653 The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself every 2 9 − 511 bits. A descrip- tion of the PN sequence and how it is generated can be found in Section 5.1 ...

Page 31

Data Sheet SERIAL PORT INTERFACE (SPI) The AD9653 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI offers the user added flexibility ...

Page 32

AD9653 HARDWARE INTERFACE The pins described in Table 17 comprise the physical interface between the user programming device and the serial port of the AD9653. The SCLK pin and the CSB pin function as inputs when using the SPI interface. ...

Page 33

Data Sheet MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02); ...

Page 34

AD9653 MEMORY MAP REGISTER TABLE The AD9653 uses a 3-wire interface and 16-bit addressing and, therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3 and Bit 4 are set to 1. When Bit ...

Page 35

Data Sheet ADDR Bit 7 (Hex) Parameter Name (MSB) Bit 6 0x0B Clock divide Open Open (global) 0x0C Enhancement Open Open control Test mode (local 0x0D User input test mode except for single sequence resets ...

Page 36

AD9653 ADDR Bit 7 (Hex) Parameter Name (MSB) Bit 6 0x18 V Open Open REF 0x19 USER_PATT1_LSB B7 B6 (global) 0x1A USER_PATT1_MSB B15 B14 (global) 0x1B USER_PATT2_LSB B7 B6 (global) 0x1C USER_PATT2_MSB B15 B14 (global) 0x21 Serial output data LVDS ...

Page 37

Data Sheet MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Interfacing to High Speed ADCs via SPI. Device Index (Register 0x05) There are certain features in the map ...

Page 38

AD9653 Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Table 21. Input Clock Phase Adjust Options Input Clock Phase Number of Input Clock Cycles of Adjust, Bits[6:4] Phase Delay 000 (Default) 0 001 1 010 2 011 3 ...

Page 39

Data Sheet APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the it is recommended that the designer become familiar with these guidelines, which describes the special circuit connections and layout requirements that are needed for certain pins. POWER ...

Page 40

... PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9653BCPZ-125 −40°C to +85°C AD9653BCPZRL7-125 −40°C to +85°C AD9653-125EBZ RoHS Compliant Part. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 7.10 0.30 7 ...

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