K4D551638F-LC40000 Samsung, K4D551638F-LC40000 Datasheet

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K4D551638F-LC40000

Manufacturer Part Number
K4D551638F-LC40000
Description
No Discount To Anyone!
Manufacturer
Samsung
Datasheet
K4D551638F-TC
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
Samsung Electronics reserves the right to change products or specification without notice.
256Mbit GDDR SDRAM
Revision 2.1
April 2005
- 1 -
256M GDDR SDRAM
Rev 2.1 (Apr. 2005)

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K4D551638F-LC40000 Summary of contents

Page 1

... K4D551638F-TC 256Mbit GDDR SDRAM INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. ...

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... Target spec defined for -TC33 Revision 1.4 (February 27, 2004) • Added K4D551638F-TC36/40 in the data sheet. • Target spec defined for -TC36/40 Revision 1.3 (December 5, 2003) • Changed VDD/VDDQ of K4D551638F-TC50 from 2. 2.6V + 0.1V Revision 1.2 (November 11, 2003) • "Wrtie-Interrupted by Read Function" is supported Revision 1.1 (October 13, 2003) • Defined ICC7 value Revision 1.0 (October 10, 2003) • ...

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... GENERAL DESCRIPTION FOR 4M x 16Bit x 4 Bank GDDR SDRAM The K4D551638F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized 4,194,304 words by 16 bits, fabricated with SAMSUNG extremely high performance up to 1.1GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications ...

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... K4D551638F-TC PIN CONFIGURATION PIN DESCRIPTION CK,CK Differential Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe CAS Column Address Strobe WE Write Enable L(U)DQS Data Strobe L(U)DM Data Mask RFU Reserved for Future Use (Top View DDQ ...

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... K4D551638F-TC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Sym- Type CK, CK*1 Input CKE Input CS Input RAS Input CAS Input WE Input LDQS,UDQS Input/Output LDM,UDM Input DQ0 ~ DQ15 Input/Output BA0, BA1 Input A0 ~ A12 Input VDD/VSS Power Supply VDDQ/VSSQ Power Supply VREF Power Supply NC/RFU No connection/ Reserved for future use *1 : The timing reference point for the differential clocking is the cross point of CK and CK ...

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... K4D551638F-TC BLOCK DIAGRAM (4Mbit x 16I Bank) Bank Select CK,CK ADDR LCKE LRAS LCBR CK,CK CKE 16 Intput Buffer CK, CK Data Input Register Serial to parallel 4Mx16 4Mx16 4Mx16 4Mx16 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS ...

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... K4D551638F-TC FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. ...

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... K4D551638F-TC MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation ...

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... K4D551638F-TC EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by assert- ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register) ...

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... IL 6. For any pin under test input of 0V < For the K4D551638F-TC60 , VDD & VDDQ =2.5V + 5%, For the K4D551638F-TC36 , VDD & VDDQ =2.8V + 0.1V and For the K4D551638F-TC33 , VDD & VDDQ = 2.8V ~ 2.95V Symbol ...

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... K4D551638F-TC DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, T Parameter Symbol Operating Current I CC1 (One Bank Active) Precharge Standby Current I P CC2 in Power-down mode Precharge Standby Current I N CC2 in Non Power-down mode Active Standby Current I P CC3 power-down mode Active Standby Current in ...

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... K4D551638F-TC AC OPERATING TEST CONDITIONS Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition Output CAPACITANCE (V =2.6V Parameter ...

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... K4D551638F-TC AC CHARACTERISTICS Parameter Symbol CK cycle time CL=3 tCK CK high level width tCH CK low level width tCL DQS out access time from CK tDQSCK Output access time from CK tAC Data strobe edge to Dout edge tDQSQ Read preamble tRPRE Read postamble tRPST CK to valid DQS-in ...

Page 14

... Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM AC CHARACTERISTICS (II) K4D551638F-TC33 Frequency Cas Latency 300MHz ( 3.3ns ) 3 K4D551638F-TC36 Frequency Cas Latency 275MHz ( 3.6ns ) 3 K4D551638F-TC40 Frequency Cas Latency 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 K4D551638F-TC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 K4D551638F-TC60 Frequency Cas Latency 166MHz ( 6.0ns ) 3 -33 -36 Min Max Min Max ...

Page 15

... K4D551638F-TC Write Interrupted by a Read & burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM ...

Page 16

... K4D551638F-TC PACKAGE DIMENSIONS (66pin TSOP-II) #66 #1 (1.50) (0.71) NOTE REFERENCE ASS’Y OUT QUALITY #34 #33 22.22±0.10 (10×) 0.65TYP 0.30±0.08 0.65±0.08 (10× 256M GDDR SDRAM Units : Millimeters (10×) (10×) +0.075 0.125 -0.035 0.10 MAX 0.25TYP [ ] 0.075 MAX 0×~8× Rev 2.1 (Apr. 2005) ...

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