24LC256T-E/SN15KV05 Microchip, 24LC256T-E/SN15KV05 Datasheet - Page 12

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24LC256T-E/SN15KV05

Manufacturer Part Number
24LC256T-E/SN15KV05
Description
24LC256 Series 256 Kb 2.5 V (32K x 8) 5 ms I2C Serial EEPROM - SOIC-8
Manufacturer
Microchip
Datasheet
24AA256/24LC256/24FC256
8.0
Read operations are initiated in much the same way as
write operations, with the exception that the R/W bit of
the control byte is set to ‘
of read operations: current address read, random read
and sequential read.
8.1
The 24XX256 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘
access was to address ‘n’ (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘
the 24XX256 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer, but does generate a Stop condition and the
24XX256 discontinues transmission (Figure 8-1).
FIGURE 8-1:
FIGURE 8-2:
FIGURE 8-3:
DS21203Q-page 12
Bus Activity
Master
SDA Line
Bus Activity
Bus Activity
Master
SDA Line
Bus Activity
x = “don’t care” bit
Bus Activity
Master
SDA Line
Bus Activity
READ OPERATION
Current Address Read
S
S
T
A
R
T
1
1
0
’. Therefore, if the previous read
S 1 0 1 0 A A A 0
S
T
A
R
T
1
Control
Byte
0 A A A 1
CURRENT ADDRESS
READ
RANDOM READ
SEQUENTIAL READ
1
2 1 0
Control
’. There are three basic types
Control
Byte
Byte
2 1 0
A
C
K
A
C
K
A
C
K
Data (n)
x
Data
Byte
High Byte
Address
N
O
A
C
K
A
C
K
1
S
T
O
P
P
’,
A
C
K
Data (n + 1)
Low Byte
Address
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24XX256 as part of a write operation (R/W bit set to
ates a Start condition following the acknowledge. This
terminates the write operation, but not before the
internal Address Pointer is set. The master then issues
the control byte again, but with the R/W bit set to a one.
The 24XX256 will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, though it does generate a
Stop condition, which causes the 24XX256 to discon-
tinue transmission (Figure 8-2). After a random Read
command, the internal address counter will point to the
address location following the one that was just read.
8.3
Sequential reads are initiated in the same way as a
random read except that after the 24XX256 transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX256 to
transmit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge,
but will generate a Stop condition. To provide sequen-
tial reads, the 24XX256 contains an internal Address
Pointer which is incremented by one at the completion
of each operation. This Address Pointer allows the
entire memory contents to be serially read during one
operation.
automatically roll over from address 7FFF to address
0000 if the master acknowledges the byte received
from the array address 7FFF.
0
’). Once the word address is sent, the master gener-
A
C
K
Random Read
Sequential Read
A
C
K
Data (n + 2)
S
T
A
R
T
S 1 0 1 0 A A A 1
The
Control
Byte
internal
2 1 0
A
C
K
 2010 Microchip Technology Inc.
A
C
K
Address
Data (n + x)
Data
Byte
Pointer
N
O
A
C
K
S
T
O
P
P
N
O
A
C
K
S
T
O
P
P
will

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