LPC2138FBD64/01-S NXP Semiconductors, LPC2138FBD64/01-S Datasheet
LPC2138FBD64/01-S
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LPC2138FBD64/01-S Summary of contents
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LPC2131/32/34/36/38 Single-chip 16/32-bit microcontrollers; 32/64/128/256/512 kB ISP/IAP flash with 10-bit ADC and DAC Rev. 04 — 16 October 2007 1. General description The LPC2131/32/34/36/38 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, that ...
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... NXP Semiconductors I One (LPC2131/32) or two (LPC2134/36/38) 8-channel 10-bit ADCs provide a total analog inputs, with conversion times as low as 2.44 s per channel. I Single 10-bit DAC provides variable analog output (LPC2132/34/36/38). I Two 32-bit timers/external event counters (with four capture and four compare channels each), PWM unit (six outputs) and watchdog ...
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... NXP Semiconductors Table 1. Type number LPC2136FBD64 LPC2136FBD64/01 LQFP64 LPC2138FBD64 LPC2138FBD64/01 LQFP64 LPC2138FHN64 LPC2138FHN64/01 HVQFN64 plastic thermal enhanced very thin quad flat 3.1 Ordering options Table 2. Type number LPC2131FBD64 LPC2131FBD64/01 LPC2132FBD64 LPC2132FBD64/01 LPC2132FHN64 LPC2132FHN64/01 LPC2134FBD64 LPC2134FBD64/01 LPC2136FBD64 LPC2136FBD64/01 LPC2138FBD64 LPC2138FBD64/01 LPC2138FHN64 LPC2138FHN64/01 LPC2131_32_34_36_38_4 ...
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... NXP Semiconductors 4. Block diagram LPC2131, LPC2131/01 LPC2132, LPC2132/01 LPC2134, LPC2134/01 LPC2136, LPC2136/01 LPC2138, LPC2138/01 P0[31:0] FAST GENERAL PURPOSE I/O P1[31:16] ARM7 local bus INTERNAL SRAM CONTROLLER 8/16/32 kB SRAM EXTERNAL EINT[3:0] INTERRUPTS 8 CAP CAPTURE/ COMPARE TIMER 0/TIMER 1 8 MAT AD0[7:0] A/D CONVERTERS 0 AND 1 (1) AD1[7:0] (2) AOUT D/A CONVERTER ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning P0.21/PWM5/CAP1.3 1 P0.22/CAP0.0/MAT0 RTCX1 4 P1.19/TRACEPKT3 RTCX2 DDA P1.18/TRACEPKT2 8 P0.25/AD0 P0.26/AD0.5 11 P0.27/AD0.0/CAP0.1/MAT0.1 P1.17/TRACEPKT1 12 P0.28/AD0.1/CAP0.2/MAT0 P0.29/AD0.2/CAP0.3/MAT0.3 P0.30/AD0.3/EINT3/CAP0.0 15 P1.16/TRACEPKT0 16 Fig 2. LPC2131 LQFP64 pinning LPC2131_32_34_36_38_4 Product data sheet ...
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... NXP Semiconductors P0.21/PWM5/CAP1.3 1 P0.22/CAP0.0/MAT0 RTCX1 P1.19/TRACEPKT3 4 RTCX2 DDA P1.18/TRACEPKT2 8 P0.25/AD0.4/AOUT 9 10 P0.26/AD0.5 11 P0.27/AD0.0/CAP0.1/MAT0.1 P1.17/TRACEPKT1 12 P0.28/AD0.1/CAP0.2/MAT0 P0.29/AD0.2/CAP0.3/MAT0.3 P0.30/AD0.3/EINT3/CAP0.0 15 P1.16/TRACEPKT0 16 Fig 3. LPC2132 LQFP64 pin configuration LPC2131_32_34_36_38_4 Product data sheet ...
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... NXP Semiconductors P0.21/PWM5/AD1.6/CAP1.3 1 P0.22/AD1.7/CAP0.0/MAT0 RTCX1 P1.19/TRACEPKT3 4 RTCX2 DDA P1.18/TRACEPKT2 8 P0.25/AD0.4/AOUT 9 10 P0.26/AD0.5 11 P0.27/AD0.0/CAP0.1/MAT0.1 P1.17/TRACEPKT1 12 P0.28/AD0.1/CAP0.2/MAT0 P0.29/AD0.2/CAP0.3/MAT0.3 P0.30/AD0.3/EINT3/CAP0.0 15 P1.16/TRACEPKT0 16 Fig 4. LPC2134/36/38 LQFP64 pin configuration LPC2131_32_34_36_38_4 ...
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... NXP Semiconductors terminal 1 index area P0.21/PWM5/AD1.6/CAP1.3 P0.22/AD1.7/CAP0.0/MAT0.0 RTCX1 P1.19/TRACEPKT3 RTCX2 DDA P1.18/TRACEPKT2 P0.25/AD0.4/AOUT P0.26/AD0.5 P0.27/AD0.0/CAP0.1/MAT0.1 P1.17/TRACEPKT1 P0.28/AD0.1/CAP0.2/MAT0.2 P0.29/AD0.2/CAP0.3/MAT0.3 P0.30/AD0.3/EINT3/CAP0.0 P1.16/TRACEPKT0 AD1.7 to AD1.0 only available on LPC2134/36/38. Fig 5. LPC2132/38 HVQFN64 pin configuration ...
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... NXP Semiconductors 5.2 Pin description Table 3. Pin description Symbol Pin P0.0 to P0.31 [1] P0.0/TXD0/ 19 PWM1 [2] P0.1/RXD0/ 21 PWM3/EINT0 [3] P0.2/SCL0/ 22 CAP0.0 [3] P0.3/SDA0/ 26 MAT0.0/EINT1 [4] P0.4/SCK0/ 27 CAP0.1/AD0.6 [4] P0.5/MISO0/ 29 MAT0.1/AD0.7 [4] P0.6/MOSI0/ 30 CAP0.2/AD1.0 [2] P0.7/SSEL0/ 31 PWM2/EINT2 [4] P0.8/TXD1/ 33 PWM4/AD1.1 [2] P0.9/RXD1/ 34 PWM6/EINT3 [4] P0.10/RTS1/ 35 CAP1.0/AD1.2 LPC2131_32_34_36_38_4 Product data sheet ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [3] P0.11/CTS1/ 37 CAP1.1/SCL1 [4] P0.12/DSR1/ 38 MAT1.0/AD1.3 [4] P0.13/DTR1/ 39 MAT1.1/AD1.4 [3] P0.14/DCD1/ 41 EINT1/SDA1 [4] P0.15/RI1/ 45 EINT2/AD1.5 [2] P0.16/EINT0/ 46 MAT0.2/CAP0.2 [1] P0.17/CAP1.2/ 47 SCK1/MAT1.2 [1] P0.18/CAP1.3/ 53 MISO1/MAT1.3 [1] P0.19/MAT1.2/ 54 MOSI1/CAP1.2 [2] P0.20/MAT1.3/ 55 SSEL1/EINT3 [4] P0.21/PWM5/ 1 AD1.6/CAP1.3 LPC2131_32_34_36_38_4 Product data sheet Type Description I CTS1 — ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [4] P0.22/AD1.7/ 2 CAP0.0/MAT0.0 [1] P0.23 58 [5] P0.25/AD0.4/ 9 AOUT [4] P0.26/AD0.5 10 [4] P0.27/AD0.0/ 11 CAP0.1/MAT0.1 [4] P0.28/AD0.1/ 13 CAP0.2/MAT0.2 [4] P0.29/AD0.2/ 14 CAP0.3/MAT0.3 [4] P0.30/AD0.3/ 15 EINT3/CAP0.0 [6] P0.31 17 P1.0 to P1.31 [6] P1.16/ 16 TRACEPKT0 [6] P1.17/ 12 TRACEPKT1 [6] P1.18/ 8 TRACEPKT2 [6] P1.19/ 4 TRACEPKT3 [6] P1.20/ 48 TRACESYNC [6] P1.21/ 44 PIPESTAT0 [6] P1.22/ 40 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [6] P1.24/ 32 TRACECLK [6] P1.25/EXTIN0 28 [6] P1.26/RTCK 24 [6] P1.27/TDO 64 [6] P1.28/TDI 60 [6] P1.29/TCK 56 [6] P1.30/TMS 52 [6] P1.31/TRST 20 [7] RESET 57 [8] XTAL1 62 [8] XTAL2 61 [8] RTCX1 3 [8] RTCX2 18, 25, 42 SSA V 23, 43, 51 ...
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... NXP Semiconductors 6. Functional description 6.1 Architectural overview The ARM7TDMI general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers ...
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... NXP Semiconductors 6.4 Memory map The LPC2131/32/34/36/38 memory map incorporates several distinct regions, as shown in Figure In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either flash memory (the default) or on-chip static RAM. This is described in “System Fig 6. LPC2131/32/34/36/38 memory map LPC2131_32_34_36_38_4 Product data sheet 6. control” ...
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... NXP Semiconductors 6.5 Interrupt controller The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... NXP Semiconductors Table 4. Block UART1 PWM0 SPI0 SSP PLL RTC System Control AD0 I2C1 BOD AD1 6.6 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals ...
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... NXP Semiconductors 6.7.2 Fast I/O features available in LPC213x/01 only • Fast I/O registers are located on the ARM local bus for the fastest possible I/O timing. • All GPIO registers are byte addressable. • Entire port value can be written in one instruction. • Mask registers allow single instruction to set or clear any number of bits in one port. ...
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... NXP Semiconductors • Built-in baud rate generator. • Standard modem interface signals included on UART1. (LPC2134/36/38 only) • The LPC2131/32/34/36/38 transmission FIFO control enables implementation of software (XON/XOFF) flow control on both UARTs and hardware (CTS/RTS) flow control on the LPC2134/36/38 UART1 only. 6.10.2 UART features available in LPC213x/01 only • ...
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... NXP Semiconductors 6.12.1 Features • Compliant with Serial Peripheral Interface (SPI) specification. • Synchronous, Serial, Full Duplex, Communication. • Combined SPI master and slave. • Maximum data bit rate of one eighth of the input clock rate. 6.13 SSP serial I/O controller The LPC2131/32/34/36/38 each contain one Serial Synchronous Port controller (SSP). ...
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... NXP Semiconductors – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Four external outputs per timer/counter corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. ...
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... NXP Semiconductors 6.17 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2131/32/34/36/38. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. ...
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... NXP Semiconductors • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard timer if the PWM mode is not enabled. • A 32-bit Timer/Counter with a programmable 32-bit Prescaler. ...
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... NXP Semiconductors The wake-up timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on ...
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... NXP Semiconductors 6.18.8 Power Control The LPC2131/32/34/36/38 support two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses ...
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... NXP Semiconductors The ARM core has a Debug Communication Channel function built-in. The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The debug communication channel is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core ...
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... NXP Semiconductors 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (core and external rail analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREF i(VREF) V analog input voltage ...
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... NXP Semiconductors 8. Static characteristics Table 6. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (core and DD external rail) V analog 3.3 V pad supply DDA voltage V input voltage on pin VBAT i(VBAT) V input voltage on pin VREF i(VREF) ...
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... NXP Semiconductors Table 6. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter I Power-down mode battery BATpd [10] supply current I active mode battery BATact [10] supply current I optimized active mode BATact(opt) battery supply [10][11] current 2 I C-bus pins V HIGH-level input voltage ...
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... NXP Semiconductors [4] V supply voltages must be present. DD [5] 3-state outputs go into 3-state mode when V [6] Accounts for 100 mV voltage drop in all supply lines. [7] Only allowed for a short time period. [8] Minimum condition for V = 4.5 V, maximum condition for V I [9] Applies to P1.16 to P1.25. [10] On pin VBAT. ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. ...
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... NXP Semiconductors Fig 8. Suggested ADC interface - LPC2131/32/34/36/38 ADx.y pin 9. Dynamic characteristics Table 8. Dynamic characteristics +85 C for commercial applications, V amb Symbol Parameter External clock f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX t clock rise time ...
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... NXP Semiconductors 9.1 Timing V Fig 9. External clock timing 9.2 LPC2138 power consumption measurements 40 I (mA Test conditions: code executed from flash; all peripherals are enabled in PCONP register; PCLK = CCLK/ (max 140 ...
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... NXP Semiconductors 15 I (mA Test conditions: Idle mode entered executing code from flash; all peripherals are enabled in PCONP register; PCLK = CCLK/ 140 C (max (typical (typical) DD Fig 11 ...
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... NXP Semiconductors 10. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 0.85 mm terminal 1 index area terminal 1 64 index area DIMENSIONS (mm are the original dimensions) A UNIT max. 0.05 0.80 0. 0.00 0.65 0.18 OUTLINE VERSION IEC SOT804 Fig 14 ...
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... NXP Semiconductors 11. Abbreviations Table 9. Acronym ADC BOD CPU DAC DCC FIFO GPIO JTAG PLL POR PWM RAM SPI SRAM SSP UART VPB LPC2131_32_34_36_38_4 Product data sheet Acronym list Description Analog-to-Digital Converter BrownOut Detection Central Processing Unit Digital-to-Analog Converter Debug Communications Channel ...
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... Product data sheet Data sheet status Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Figure 1: changed incorrect character font Figure 5: added fi ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Enhancements brought by LPC213x/01 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Key features common for LPC213x and LPC213x/ Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Functional description . . . . . . . . . . . . . . . . . . 13 6.1 Architectural overview 6.2 On-chip flash program memory . . . . . . . . . . . 13 6 ...