FST16232MTDX Fairchild Semiconductor, FST16232MTDX Datasheet
FST16232MTDX
Specifications of FST16232MTDX
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FST16232MTDX Summary of contents
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... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Diagram © 1999 Fairchild Semiconductor Corporation Features 4 switch connection between two ports. Minimal propagation delay through the switch. ...
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Connection Diagram www.fairchildsemi.com Pin Descriptions Pin Name Description Control Pins 1 0 CLK Clock Input CLKEN Clock Enable Input 1A, 2A Bus A 1B, 2B Bus B Truth Table Inputs S S CLK CLKEN ...
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Absolute Maximum Ratings Supply Voltage ( Switch Voltage ( Input Voltage (V )(Note Input Diode Current ( Output (I ) Sink Current OUT DC V ...
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AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX Prop Delay Bus to Bus (Note 6) PHL PLH Prop Delay CLK PHL PLH Output Enable Time ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A 5 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Technology Description The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its 74LVX3L384 ...