SST25VF040B-50-4C-S2AF-T Silicon Storage Tech, SST25VF040B-50-4C-S2AF-T Datasheet
SST25VF040B-50-4C-S2AF-T
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SST25VF040B-50-4C-S2AF-T Summary of contents
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... Erase or Program operation is less than alternative flash memory technologies. The SST25VF040B device is offered in an 8-lead SOIC (200 mils), 8-lead SOIC (150 mils), and 8-contact WSON (6mm x 5mm) packages. See Figure 2 for pin assignments. ...
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... Data Sheet Address Buffers and Latches CE# FIGURE 1: Functional Block Diagram ©2007 Silicon Storage Technology, Inc Decoder Control Logic Serial Interface SCK SI SO WP# HOLD Mbit SPI Serial Flash SST25VF040B SuperFlash Memory Y - Decoder I/O Buffers and Data Latches 1295 B1.0 S71295-02-000 7/07 ...
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... The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device. V Power Supply To provide power supply voltage: 2.7-3.6V for SST25VF040B DD V Ground SS ©2007 Silicon Storage Technology, Inc ...
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... FIGURE 3: SPI Protocol ©2007 Silicon Storage Technology, Inc. 4 Mbit SPI Serial Flash The SST25VF040B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
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... HOLD# Active FIGURE 4: Hold Condition Waveform Write Protection SST25VF040B provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL) in the status register pro- vide Write protection to the memory array and the status register ...
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... Default at Power- Auto Address Increment (AAI) The Auto Address Increment Programming-Status bit pro- vides status on whether the device is in AAI programming mode or Byte-Program mode. The default at power up is Byte-Program mode. 6 SST25VF040B Read/Write R R R/W R/W R/W R/W R R/W T3.0 1295 S71295-02-000 7/07 ...
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... Lock-Down (BPL) bit. When BPL is set prevents any further alteration of the BPL, BP3, BP2, BP1, and BP0 bits. When the WP# pin is driven high (V effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. SST25VF040B FOR 2 Status Register Bit BP3 ...
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... Data Sheet Instructions Instructions are used to read, write (Erase and Program), and configure the SST25VF040B. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instruc- tions, the Write-Enable (WREN) instruction must be exe- cuted first ...
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... Mbit SPI Serial Flash SST25VF040B Read (25 MHz) The Read instruction, 03H, supports MHz Read. The device outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high tran- sition on CE#. The internal address pointer will automati- cally increment until the highest memory address is reached ...
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... ADD. ADD. ADD. X MSB D MSB Mbit SPI Serial Flash SST25VF040B N+1 N+2 N+3 N OUT OUT OUT OUT OUT 1295 HSRdSeq ...
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... Mbit SPI Serial Flash SST25VF040B Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a pro- tected memory area will be ignored. ...
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... AAI-Word-program opera- tion and return SO pin to output Software Status Register =1. CE# must be 0 data during AAI Word programming. (see Figure 9) CE# SCK 12 4 Mbit SPI Serial Flash SST25VF040B MODE MODE MSB HIGH IMPEDANCE SO 1295 EnableSO ...
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... Mbit SPI Serial Flash SST25VF040B CE# MODE SCK MODE MSB HIGH IMPEDANCE SO 1295 DisableSO.0 FIGURE 9: Disable SO as Hardware RY/BY# during AAI Programming CE SCK REN SI Load AAI command, Address, 2 bytes data SO Note: 1. Valid commands during AAI programming: AAI command or WRDI command 2 ...
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... FIGURE 11: Auto Address Increment (AAI) Word-Program Sequence with Software End-of-Write Detection ©2007 Silicon Storage Technology, Inc. Check for Flash Busy Status to load next valid command Mbit SPI Serial Flash SST25VF040B WRDI RDSR n-1 n Last 2 WRDI to exit ...
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... Mbit SPI Serial Flash SST25VF040B 4-KByte Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence ...
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... MSB HIGH IMPEDANCE ADDR ADDR MSB MSB HIGH IMPEDANCE 16 4 Mbit SPI Serial Flash SST25VF040B ), remaining address bits can X CE# must be driven high before the instruction -A ]. Address bits [ are used remaining address bits can ...
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... Mbit SPI Serial Flash SST25VF040B Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence ...
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... Any pro- gram operation in progress may continue executing the WRDI instruction. CE# must be driven high before the WRDI instruction is executed. CE# MODE MODE 0 SCK 04 SI MSB HIGH IMPEDANCE SO 1295 WRDI Mbit SPI Serial Flash SST25VF040B after BP S71295-02-000 7/07 ...
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... Mbit SPI Serial Flash SST25VF040B Write-Status-Register (WRSR) The Write-Status-Register instruction writes new values to the BP3, BP2, BP1, BP0, and BPL bits of the status regis- ter. CE# must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 19 for EWSR or WREN and WRSR instruction sequences ...
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... Data Sheet JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as SST25VF040B and the manufacturer as SST. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin ...
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... Mbit SPI Serial Flash SST25VF040B Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as SST25VF040B and manufacturer as SST. This command is backward compatible to all SST25xFxxxA devices and should be used as default device identification when multi- ple versions of SPI Serial Flash devices are used in a design ...
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... OUT =100 µ 0 =1 =-100 µ Mbit SPI Serial Flash SST25VF040B +0.5V DD +2. EST = /0.9 V @25 MHz, SO=open DD DD /0.9 V @50 MHz, SO=open Max ...
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... Mbit SPI Serial Flash SST25VF040B TABLE 10: Capacitance (T = 25°C, f=1 Mhz, other pins open) A Parameter Description 1 C Output Pin Capacitance OUT 1 C Input Capacitance IN 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ...
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... CE# T SCKH SCK T CLZ SO SI FIGURE 23: Serial Output Timing Diagram ©2007 Silicon Storage Technology, Inc. T SCKF T SCKR T SCKL T OH MSB Mbit SPI Serial Flash SST25VF040B T CPH T T CEH CHS LSB HIGH-Z 1295 SerIn.0 T CHZ LSB 1295 SerOut.0 S71295-02-000 7/07 ...
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... Mbit SPI Serial Flash SST25VF040B CE# SCK SO SI HOLD# FIGURE 24: Hold Timing Diagram Max DD Chip selection is not allowed. Commands may not be accepted or properly interpreted by the device. V Min DD FIGURE 25: Power-up Timing Diagram ©2007 Silicon Storage Technology, Inc HHH HLS T HLH T HZ ...
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... V (0.1V DD ILT DD ) and V (0.4V ). Input rise and fall times (10 TESTER TO DUT 26 4 Mbit SPI Serial Flash SST25VF040B V HT OUTPUT V LT 1295 IORef.0 ) for a logic “0”. Measurement reference points ↔ 90%) are <5 ns. Note Test HT HIGH ...
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... XX XX XXX X - Valid combinations for SST25VF040B SST25VF040B-50-4C-S2AF SST25VF040B-50-4I-S2AF Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2007 Silicon Storage Technology, Inc. ...
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... Maximum allowable mold flash is 0. the package ends and 0.25 mm between leads. FIGURE 28: 8-Lead Small Outline Integrated Circuit (SOIC) 200 mil Body Width (5.2mm x 8mm) SST Package Code: S2A ©2007 Silicon Storage Technology, Inc. 4 Mbit SPI Serial Flash SIDE VIEW 0.50 0.35 1.27 BSC 0.25 END VIEW 0.05 2.16 1.75 0.25 0.19 08-soic-EIAJ-S2A-3 28 SST25VF040B 0˚ 8˚ 0.80 0.50 1mm S71295-02-000 7/07 ...
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... Mbit SPI Serial Flash SST25VF040B Pin #1 Identifier TOP VIEW 5.0 4.8 4.00 3.80 6.20 5.80 Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends and 0.25 mm between leads. ...
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... Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2007 Silicon Storage Technology, Inc. SIDE VIEW 0.2 5.00 ± 0.10 0.076 0.05 Max 0.80 0.70 leads. 1mm SS of the unit. SS Description www.SuperFlash.com or www.sst.com 30 4 Mbit SPI Serial Flash SST25VF040B BOTTOM VIEW Pin #1 1.27 BSC 4.0 0.48 0.35 3.4 0.70 0.50 CROSS SECTION 0.80 0.70 8-wson-5x6-QA-9.0 Date Sep 2005 Jan 2006 Jul 2007 ...