9P935AGLF IDT, 9P935AGLF Datasheet

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9P935AGLF

Manufacturer Part Number
9P935AGLF
Description
Delay Lines / Timing Elements
Manufacturer
IDT
Datasheet

Specifications of 9P935AGLF

Product Category
Delay Lines / Timing Elements
Rohs
yes
Part # Aliases
ICS9P935AGLF

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Part Number
Manufacturer
Quantity
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Part Number:
9P935AGLF
Manufacturer:
ICS
Quantity:
327
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
Description
DDR I/DDR II Zero Delay Clock Buffer
Output Features
Key Specifications
Funtional Block Diagram
IDT
TM
CYCLE - CYCLE jitter: <100ps
OUTPUT - OUTPUT skew: <100ps
DUTY CYCLE: 48% - 52%
28-pin SSOP package
Available in RoHS compliant packaging
Operates @ 2.5V or 1.8V
Low skew, low jitter PLL clock driver
Max frequency supported = 400MHz (DDRII 800)
I
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Programmable skew through SMBus
Frequency defect control thorugh SMBus
Individual output control programmable through SMBus
/ICS
2
C for functional and output control
TM
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
CLK_INC
CLK_INT
SDATA
FB_IN
SCLK
Control
Logic
PLL
1
Pin Configuration
VDDA2.5/1.8 7
VDD2.5/1.8 3
VDD2.5/1.8 11
CLK_INC 10
CLK_INT 9
DDRC0 1
DDRC1 5
DDRC2 13
DDRT0 2
DDRT1 4
DDRT2 12
GND 6
GND 8
GND 14
28-SSOP/TSSOP
FB_OUT
DDRT0
DDRC0
DDRT1
DDRC1
DDRT2
DDRC2
DDRT3
DDRC3
DDRT4
DDRC4
DDRT5
DDRC5
ICS9P935
DATASHEET
28 GND
27 DDRC5
26 DDRT5
25 VDD2.5/1.8
24 GND
23 DDRC4
22 DDRT4
21 VDD2.5/1.8
20 SDATA
19 SCLK
18 FB_IN
17 FB_OUT
16 DDRT3
15 DDRC3
ICS9P935
REV H 12/1/08

Related parts for 9P935AGLF

9P935AGLF Summary of contents

Page 1

... DUTY CYCLE: 48% - 52% • 28-pin SSOP package • Available in RoHS compliant packaging • Operates @ 2.5V or 1.8V Funtional Block Diagram SCLK SDATA FB_IN CLK_INT CLK_INC DDR I/DDR II Phase Lock Loop Zero Delay Buffer IDT TM /ICS TM Pin Configuration DDRC0 1 DDRT0 2 VDD2.5/1.8 3 DDRT1 4 DDRC1 5 GND 6 VDDA2.5/1.8 7 GND 8 CLK_INT 9 CLK_INC 10 VDD2 ...

Page 2

... GND 25 VDD2.5/1.8 26 DDRT5 27 DDRC5 28 GND DDR I/DDR II Phase Lock Loop Zero Delay Buffer TM TM IDT /ICS Type Pin Description OUT "Complementary" Clock of differential pair output. OUT "True" Clock of differential pair output. PWR Power supply, nominal 2.5V or 1.8V OUT "True" Clock of differential pair output. ...

Page 3

... OH voltage Low-level output voltage Input Capacitance Output Capacitance OUT DDR I/DDR II Phase Lock Loop Zero Delay Buffer TM TM IDT /ICS -0.5V to 2.7V GND –0 0°C to +70°C 115°C –65°C to +150°C CONDITIONS GND GND ...

Page 4

... VTR is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations which the differential signal must be crossing. DDR I/DDR II Phase Lock Loop Zero Delay Buffer TM TM IDT /ICS SYMBOL CONDITIONS DDQ VDD ...

Page 5

... This is due to the formula: duty cycle=t decreases as the frequency goes up. 3. Switching characteristics guaranteed for application frequency range. 4. Static phase offset shifted by design. DDR I/DDR II Phase Lock Loop Zero Delay Buffer TM TM IDT /ICS CONDITIONS freq 1.8V+0.1V @ 25°C op freq 1.8V+0.1V @ 25°C App ...

Page 6

... Input Clamp Voltage V IK High-level output V OH voltage Low-level output voltage Input Capacitance Output Capacitance OUT DDR I/DDR II Phase Lock Loop Zero Delay Buffer TM TM IDT /ICS , V = 2.5V ± 0.2V VDD DD CONDITIONS GND GND 0pf @ 200MHz L C ...

Page 7

... VT is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations which the differential signal must be crossing. DDR I/DDR II Phase Lock Loop Zero Delay Buffer TM TM IDT /ICS CONDITIONS VDD DDRT,DDRC IL DDRT,DDRC ...

Page 8

... This is due to the formula: duty cycle=t decreases as the frequency goes up. 3. Switching characteristics guaranteed for application frequency range. 4. Static phase offset shifted by design. DDR I/DDR II Phase Lock Loop Zero Delay Buffer TM TM IDT /ICS , V = 2.5 V +/- 0.2V (unless otherwise stated) VDD DD CONDITIONS SYMBOL freq o 2 ...

Page 9

... ACK Byte ACK P stoP bit Notes: 1. The IDT clock generator is a slave/receiver, I Read-Back will support SMBus block read protocol. 2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) 3. The input is operating at 3.3V logic levels. 4. The data byte format is 8 bit bytes. ...

Page 10

... N/A N/A N/A 10 N/A N/A N/A 01 N/A N/A N/A 00 MSB DDR I/DDR II Phase Lock Loop Zero Delay Buffer TM TM IDT /ICS Control Function Type Low Frequency Detect RW PLL OFF Control FB_OUT Control RW Output Control RW Output Control RW Output Control RW Output Control RW Output Control RW Output Control RW Control Function ...

Page 11

... E1 INDEX INDEX AREA AREA 209 mil SSOP Ordering Information ICS9P935yFLF-T Example: ICS XXXX y F LF- T DDR I/DDR II Phase Lock Loop Zero Delay Buffer TM TM IDT /ICS c SYMBOL VARIATIONS - SEATING ...

Page 12

... DDR I/DDR II Phase Lock Loop Zero Delay Buffer Ordering Information ICS9P935yGLF-T Example: ICS XXXX y G LF- T DDR I/DDR II Phase Lock Loop Zero Delay Buffer TM TM IDT /ICS SYMBOL VARIATIONS Reference Doc.: JEDEC Publication 95, MO-153 10-0035 Designation for tape and reel packaging RoHS Compliant (Optional) ...

Page 13

... U.S.) © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated TM Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners ...

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