8N3Q001EG-1033CDI IDT, 8N3Q001EG-1033CDI Datasheet

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8N3Q001EG-1033CDI

Manufacturer Part Number
8N3Q001EG-1033CDI
Description
Programmable Oscillators
Manufacturer
IDT
Series
IDT8Nr
Datasheet

Specifications of 8N3Q001EG-1033CDI

Package / Case
5 mm x 7 mm x 1.5 mm
Frequency
15.476 MHz to 866.67, 975 MHz to 1300 MHz
Frequency Stability
+/- 50 PPM
Supply Voltage
3.63 V
Load Capacitance
10 pF
Termination Style
SMD/SMT
Output Format
LVPECL
Minimum Operating Temperature
- 40 C
Maximum Operating Temperature
+ 85 C
Dimensions
7 mm W x 5 mm L x 1.5 mm H
Product
VCXO
Supply Voltage - Max
3.465 V
Supply Voltage - Min
3.135 V
Part # Aliases
IDT8N3Q001EG-1033CDI
General Description
The IDT8N3Q001 is a Quad-Frequency Programmable Clock
Oscillator with very flexible frequency programming capabilities. The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum of high clock frequency and low phase noise
performance. The device accepts 2.5V or 3.3V supply and is
packaged in a small, lead-free (RoHS 6) 10-lead Ceramic 5mm x
7mm x 1.55mm package.
Besides the four default power-up frequencies set by the FSEL0 and
FSEL1 pins, the IDT8N3Q001 can be programmed via the I
interface to output clock frequencies between 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz to a very high degree of
precision with a frequency step size of 435.9Hz ÷ N (N is the PLL
output divider). Since the FSEL0 and FSEL1 pins are mapped to 4
independent PLL M and N divider registers (P, MINT, MFRAC and N),
reprogramming those registers to other frequencies under control of
FSEL0 and FSEL1 is supported. The extended temperature range
supports wireless infrastructure, telecommunication and networking
end equipment requirements.
IDT8N3Q001GCD REVISION A MARCH 6, 2012
Block Diagram
SDATA
FSEL1
FSEL0
SCLK
OE
Pulldown
Pulldown
Pullup
Pullup
Pullup
f
XTAL
OSC
Quad-Frequency Programmable XO IDT8N3Q001 REV G
÷P
2
PFD
LPF
&
÷MINT, MFRAC
Configuration Register (ROM)
(Frequency, APR, Polarity)
I
2
C Control
FemtoClock® NG
1950-2600MHz
25
VCO
2
C
1
Features
÷N
Fourth generation FemtoClock® NG technology
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
Four power-up default frequencies (see part number order
codes), re-programmable by I
internal PLL control registers
Frequency programming resolution is 435.9Hz ÷N
One 2.5V, 3.3V LVPECL clock output
Two control inputs for the power-up default frequency
LVCMOS/LVTTL compatible control inputs
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.244ps
(typical), integer PLL feedback configuration
RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.265ps
(typical), integer PLL feedback configuration
Full 2.5V or 3.3V supply modes
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
I
2
7
C programming interface for the output clock frequency and
Q
nQ
10-lead Ceramic 5mm x 7mm x 1.55mm
Pin Assignment
2
C
DNU 1
V
OE 2
EE
package body
©2012 Integrated Device Technology, Inc.
IDT8N3Q001
CD Package
3
Top View
8 V
7 nQ
6 Q
DATA SHEET
CC

Related parts for 8N3Q001EG-1033CDI

8N3Q001EG-1033CDI Summary of contents

Page 1

... Ceramic 5mm x 7mm x 1.55mm package. Besides the four default power-up frequencies set by the FSEL0 and FSEL1 pins, the IDT8N3Q001 can be programmed via the I interface to output clock frequencies between 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz to a very high degree of precision with a frequency step size of 435.9Hz ÷ ...

Page 2

... NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of 218Hz or better. IDT8N3Q001GCD REVISION A MARCH 6, 2012 Type Description Do not use. Output enable pin. See Table 3 for function. LVCMOS/LVTTL interface Input Pullup levels ...

Page 3

... Block Diagram with Programming Registers OSC f XTAL Control Pullup SCLK Pullup SDATA Pulldown FSEL[1:0] 2 Pullup OE IDT8N3Q001GCD REVISION A MARCH 6, 2012 PFD FemtoClock® NG ÷P & LPF 1950-2600MHz 2 Feedback Divider M (25 Bit) MINT  MFRAC  (7 bits) (18 bits)   7 Programming Registers ...

Page 4

... The four configuration registers for the P, M (MINT & MFRAC) and N dividers which are named Pn, MINTn, MFRACn and Nn with n “n” denominates one of the four possible configurations. IDT8N3Q001GCD REVISION A MARCH 6, 2012 rd overtone crystal and As identified previously, the configurations (MINT & MFRAC) of either 114 ...

Page 5

... Voltage FSEL[1: Input I SDATA, SCLK IH High Current FSEL0, FSEL1 OE Input I SDATA, SCLK IL Low Current FSEL0, FSEL1 IDT8N3Q001GCD REVISION A MARCH 6, 2012 . Rating 3.63V -0. 10mA  50mA 100mA 49.4C/W (0 mps) -65C to 150C 3.3V ± 5 Test Conditions 2.5V ± ...

Page 6

... Carrier Single-side band phase noise,   (1k) N 1kHz from Carrier Single-side band phase noise,   (10k) N 10kHz from Carrier IDT8N3Q001GCD REVISION A MARCH 6, 2012 = 3.3V ± 2.5V ± 5 Test Conditions to V – 2V 3.3V ± 2.5V ± 5 ...

Page 7

... NOTE 3: Please see the FemtoClockNG Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the optimum configuration for phase noise. Integer PLL feedback is the default operation for the dddd = 1xxx order codes and configures DSM_ENA = 0 and ADC_EN = 0. NOTE 4: Integration range: 12kHz-20MHz. NOTE 5: Integration range: 1kHz-40MHz. IDT8N3Q001GCD REVISION A MARCH 6, 2012 Test Conditions Minimum 156.25MHz 156.25MHz 156 ...

Page 8

... IDT8N3Q001 REV G Data Sheet Typical Phase Noise at 156.25MHz (12kHz - 20MHz) NOTE: RMS Phase Noise (Random) for Integer PLL Feedback and f IDT8N3Q001GCD REVISION A MARCH 6, 2012 Offset Frequency (Hz) =100.000MHz. XTAL 8 QUAD-FREQUENCY PROGRAMMABLE-XO ©2012 Integrated Device Technology, Inc. ...

Page 9

... Offset Frequency f 1 RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers RMS Phase Jitter nQ 80% 20 Output Rise/Fall Time IDT8N3Q001GCD REVISION A MARCH 6, 2012 2V SCOPE V Qx nQx V -0.5V± 0.125V 2.5V LVPECL Output Load AC Test Circuit f 2 Reference Point (Trigger Edge) ...

Page 10

... The FSEL[1:0] pins have internal pulldowns and OE control pins have internal pullups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. SCLK and SDATA should be left floating if not used. IDT8N3Q001GCD REVISION A MARCH 6, 2012 x 100% 10 QUAD-FREQUENCY PROGRAMMABLE-XO ...

Page 11

... Figure 1A. 3.3V LVPECL Output Termination IDT8N3Q001GCD REVISION A MARCH 6, 2012 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 1A and 1B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may ...

Page 12

... LVPECL Driver Figure 2A. 2.5V LVPECL Driver Termination Example V = 2.5V CC 50Ω 50Ω 2.5V LVPECL Driver Figure 2C. 2.5V LVPECL Driver Termination Example IDT8N3Q001GCD REVISION A MARCH 6, 2012 level. The R3 in Figure 2B can be eliminated and the termination is shown in Figure 2C. – very close to ground 2.5V 2.5V R3 250Ω + – ...

Page 13

... IDT8N3Q001 REV G Data Sheet Schematic Layout Figure 3 shows an example of IDT8N3Q001 application schematic. In this example, the device is operated at V high speed analog circuitry, the power supply pins are vulnerable to noise. To achieve optimum jitter performance, power supply isolation is required. The IDT8N3Q001 provides separate power supplies to isolate from coupling into the internal PLL ...

Page 14

... Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the IDT8N3Q001 is the sum of the core power plus the power dissipated in the load(s).  The following is the power dissipation for V NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. ...

Page 15

... Pd_H = [(V – (V – 2V))/R OH_MAX CC_MAX [(2V – 0.8V)/50] * 0.8V = 19.2mW Pd_L = [(V – (V – 2V))/R OL_MAX CC_MAX [(2V – 1.5V)/50] * 1.5V = 15mW Total Power Dissipation per output pair = Pd_H + Pd_L = 34.2mW IDT8N3Q001GCD REVISION A MARCH 6, 2012 V OUT RL 50Ω – 0.8V CC_MAX = V – 1.5V ...

Page 16

... Multi-Layer PCB, JEDEC Standard Test Boards NOTE: For proper thermal dissipation, the PCB layout for the pin pad should at minimum equal the package pin dimensions. Transistor Count The transistor count for IDT8N3Q001 Rev G is: 47,372 IDT8N3Q001GCD REVISION A MARCH 6, 2012  vs. Air Flow ...

Page 17

... IDT8N3Q001 REV G Data Sheet Package Outline and Package Dimensions IDT8N3Q001GCD REVISION A MARCH 6, 2012 QUAD-FREQUENCY PROGRAMMABLE-XO 17 ©2012 Integrated Device Technology, Inc. ...

Page 18

... The device options, default frequencies and default VCXO pull range must be specified at the time of order and are programmed by IDT before the shipment. Shown below are the available order codes, including the device options and default frequency configurations. Example part number: the order code 8N3QV01FG-0001CDI specifies a programmable, quad default-frequency VCXO with a voltage supply of 2 ...

Page 19

... Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments ...

Page 20

... IDT8N3Q001 REV G Data Sheet Revision History Sheet Rev Table Page Description of Change Table 9 Device Marking, corrected marking. IDT8N3Q001GCD REVISION A MARCH 6, 2012 QUAD-FREQUENCY PROGRAMMABLE-XO 20 Date 3/6/12 ©2012 Integrated Device Technology, Inc. ...

Page 21

... IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT ...

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