DS1267BS-010+ Maxim Integrated, DS1267BS-010+ Datasheet
DS1267BS-010+
Specifications of DS1267BS-010+
Related parts for DS1267BS-010+
DS1267BS-010+ Summary of contents
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... Cascade Port Output OUT V - +5V Supply CC GND - Ground Internal Connection PIN- PART NO. PACKAGE DS1267BE-010+ 20 TSSOP DS1267BE-050+* 20 TSSOP DS1267BE-100+* 20 TSSOP DS1267BS-010 DS1267BS-050 DS1267BS-100 *Future Product—Contact factory for availability 19-6589; Rev 0; 1/13 Dual Digital Potentiometer PIN ASSIGNMENT ...
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... Bit 1 contains the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper setting. Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position, with the MSB for the wiper position occupying bit 9 and the LSB bit 16. Maxim Integrated ............................................................................................................................................................................................. 2 must be high to begin any communication to the DS1267B. The CLK DS1267B ...
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... I/O shift register are loaded into the respective multiplexers for setting wiper position. A new wiper position will only engage after a the DS1267B wiper positions will be set at 50% of the total resistance or binary value 1000 0000. Maxim Integrated ............................................................................................................................................................................................. 3 signal input should be taken to a low RST RST transition to the inactive state ...
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... CASCADE OPERATION A feature of the DS1267B is the ability to control multiple devices from a single processor. Multiple DS1267Bs can be linked or daisy-chained as shown in Figure data bit is entered into the I/O shift register of the DS1267B a bit will appear at the C The stack select bit of the DS1267B will always be the first out the part at the beginning of a transaction. ...
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... When the CLK input transitions low to high, bit 17 is loaded into the first position of the I/O shift register and bit 16 becomes present bits (or 17 times the number of DS1267Bs in the daisy chain), the data has shifted completely around and back to its original position. When same as before the read occurred) is loaded into the wiper-0, wiper-1, and stack select bit I/O register ...
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... Figure 7 presents the device connected in an inverting variable gain amplifier. The gain of the circuit on Figure 7 is given by the following equation: Maxim Integrated ............................................................................................................................................................................................. 6 Linearity vs. Tap Position DNL INL ...
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... Figure 8 shows the device operating in a fixed gain attenuator where the potentiometer is used to attenuate an incoming signal. Note the resistance R1 is chosen to be much greater than the wiper resistance to minimize its effect on circuit gain. INVERTING VARIABLE GAIN AMPLIFIER Figure 7 FIX GAIN ATTENUATOR Figure 8 Maxim Integrated ............................................................................................................................................................................................. 7 ...
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... RECOMMENDED DC OPERATING CONDITIONS PARAMETER Supply Voltage Input Logic 1 Input Logic 0 Substrate Bias Resistor Inputs DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Current Input Leakage Wiper Resistance Wiper Current Logic 1 Output at 2.4V Logic 0 Output at 0.4V Standby Current Maxim Integrated ............................................................................................................................................................................................. 8 = GND) .......................................................... -0.5V to +7. -5.5V ............................................................... -5. SYMBOL MIN TYP ...
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... INL is used to determine wiper voltage versus expected voltage as determined by wiper position. 4. DNL is used to determine the change in voltage between successive tap positions active regardless of the state of OUT 6. See Figures 9(a), (b), and (c). 7. See Figure 11. 8. Valid at +25°C only. 9. Digital Inputs Maxim Integrated ............................................................................................................................................................................................. 9 SYMBOL MIN -20 -1.6 -0.5 SYMBOL MIN TYP ...
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... TIMING DIAGRAMS Figure 9 (A) 3-WIRE SERIAL INTERFACE GENERAL OVERVIEW (B) START OF COMMUNICATION TRANSACTION Maxim Integrated ........................................................................................................................................................................................... 10 ...
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... END OF COMMUNICATION TRANSACTION TYPICAL SUPPLY CURENT VS. SERIAL CLOCK RATE Figure 11 Maxim Integrated ........................................................................................................................................................................................... 11 ...
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... RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE TSSOP Maxim Integrated ........................................................................................................................................................................................... 12 PACKAGE CODE DOCUMENT NO. W16+6 21-0042 U20+2 ...
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... Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed ...