IS43DR32800A-37CBLI-TR ISSI, IS43DR32800A-37CBLI-TR Datasheet

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... IS43DR32800A, IS43/46DR32801A 8Mx32           256Mb DDR2 DRAM FEATURES • 1.8V ±0.1V 1.8V ±0.1V dd ddq • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 internal banks for concurrent operation • Programmable CAS latency (CL and 6 supported • ...

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... IS43DR32800A, IS43/46DR32801A GENERAL DESCRIPTION Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0-BA1 select the bank; A0-A11/A12 select the row and A0-A7/A8 select the column). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the auto precharge command issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. FUNCTIONAL  ...

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... IS43DR32800A, IS43/46DR32801A PIN DESCRIPTION TABLE Symbol  Type  Function  Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. CK, CK Input Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates, internal clock signals and device input buffers and output drivers. Taking CKE LOW provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry ...

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... IS43DR32800A, IS43/46DR32801A Symbol  Type  Function  Input/ DQ0-31 Data Input/Output: Bi-directional data bus. Output Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobes DQS(n) may be used in single ended mode or paired with optional complementary signals DQS(n) to provide differential pair signaling to the system during both reads and writes. A control bit at EMR(1)[A10] enables or disables all complementary data strobe signals. DQS, (DQS) Input/ (DQS 0-3, Output DQS 0-3) DQS0 corresponds to the data on DQ0-DQ7 ...

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... IS43DR32800A, IS43/46DR32801A PIN CONFIGURATION  126-ball BGA for x32 (Top View) (11mm x 14mm Body, 0.8mm Ball Pitch) PACKAGE CODE VDD B DQ1 C VSSQ D DQ4 E VSSQ F DQ7 CAS DQ23 M VSSQ N DQ20 P VSSQ R DQ17 S VDD Pin name Function A0 to A12 Address inputs BA0, BA1 ...

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... IS43DR32800A, IS43/46DR32801A ELECTRICAL SPECIFICATIONS Absolute Maximum DC Ratings Symbol  Parameter  V Voltage on VDD pin relative to Vss dd V Voltage on VDDQ pin relative to Vss ddq V Voltage on VDDL pin relative to Vss ddl Voltage on any pin relative to Vss in out T Storage Temperature stg Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

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... IS43DR32800A, IS43/46DR32801A Operating Temperature Condition Symbol Parameter Commercial Temperature Industrial Temperature, TOPER Automotive Temperature (A1) Automotive Temperature (A2) Notes Operating case temperature at center of package Operating ambient temperature immediately above package center Both temperature specifications must be met. Thermal Resistance Package Substrate (Airflow = 0m/s) 126-ball WBGA 4-layer ODT DC Electrical Characteristics PARAMETER/CONDITION  R effective impedance value for EMRS(1)[A6,A2]=0,1; 75 Ω effective impedance value for EMRS(1)[A6,A2]=1,0; 150 Ω ...

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... IS43DR32800A, IS43/46DR32801A Input DC logic level Symbol  Parameter VIH(dc) dc input logic HIGH VIL(dc) dc input logic LOW Input AC logic level Symbol Parameter VIH (ac) ac input logic HIGH VREF + 0.250 VIL (ac) ac input logic LOW VSSQ - Vpeak Notes: 1. Refer to Overshoot/undershoot specifications for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot. AC Input Test Conditions Symbol Condition VREF Input reference voltage VSWING(MAX) Input signal maximum peak to peak swing ...

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... IS43DR32800A, IS43/46DR32801A Differential input AC Logic Level Symbol Parameter VID (ac) ac differential input voltage VIX (ac) ac differential crosspoint voltage Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS and VCP is the complementary input signal (such DQS). The minimum value is equal to VIH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ ...

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... IS43DR32800A, IS43/46DR32801A OVERShOOT/UNDERShOOT SPECIFICATION AC overshoot/undershoot specification for Address and Control pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDD (see figure below) Maximum undershoot area below VSS (see figure below) Maximum Amplitude V DD Volts V SS (V) Maximum Amplitude AC overshoot and undershoot definition for address and control pins AC overshoot/undershoot specification for Clock, Data, Strobe, and Mask pins: DQ, DQS, DQS, DM, CK, CK Parameter ...

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... IS43DR32800A, IS43/46DR32801A Output Buffer Characteristics Output AC Test Conditions Symbol Parameter VOTR Output Timing Measurement Reference Level Output DC Current Drive Symbol Parameter IOH(dc) Output Minimum Source DC Current IOL(dc) Output Minimum Sink DC Current Notes: 1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 Ω for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 Ω for values of VOUT between 0 V and 280 mV. ...

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... IS43DR32800A, IS43/46DR32801A IDD Specifications & Test Conditions Conditions Symbol     IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH HIGH between valid commands; 50% of Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD1 Operating one bank active-read-precharge current; IOUT = 0mA CL(IDD tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); ...

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... IS43DR32800A, IS43/46DR32801A IDD Specifications & Test Conditions (continued) Conditions Symbol     IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0 mA CL(IDD tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH HIGH between valid commands; 50% of Address bus inputs are SWITCHING; Data pattern is same as IDD4W IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; ...

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... IS43DR32800A, IS43/46DR32801A IDD testing parameters Speed DDR2-533 DDR2-400 Bin(CL-tRCD-tRP) 4-4-4 CL(IDD) 4 tRCD(IDD) 15 tRC(IDD) 60 tRRD(IDD) 7.5 tCK(IDD) 3.75 tRASmin(IDD) 45 tRASmax(IDD) 70 tRP(IDD) 15 tRFC(IDD Units 3-3-3 3 tCK 7 Integrated Silicon Solution, Inc. — www.issi.com Rev.  00E 09/08/2010 ...

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... IS43DR32800A, IS43/46DR32801A Input/Output Capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS Electrical Characteristics & AC Timing Specifications Refresh parameters (TOPER; VDDQ = 1.8 V +/- 0.1 V; VDD = 1.8 V +/- 0.1 V) Parameter Refresh to active/Refresh command time Average periodic refresh interval Notes: 1 ...

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... IS43DR32800A, IS43/46DR32801A Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) (For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.) Parameter Clock cycle time, CL=x CK HIGH pulse width CK LOW pulse width DQS latching rising transitions to associated clock edges DQS falling edge to CK setup time DQS falling edge hold time from CK DQS input HIGH pulse width DQS input LOW pulse width Write preamble Write postamble Address and control input setup time Address and control input hold time Address and control input setup time Address and control input hold time Control & Address input pulse width for each input DQ and DM input setup time DQ and DM input hold time DQ and DM input setup time (differential strobe) ...

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... IS43DR32800A, IS43/46DR32801A Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) cont'd (For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.) Parameter Active to active command period CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay tRTP CKE minimum pulse width (HIGH and LOW pulse width) Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non- read command ...

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... IS43DR32800A, IS43/46DR32801A Guidelines for AC Parameters 1. DDR2 SDRAM AC Timing Reference Load Figure "AC Timing Reference Load" represents the timing reference load used in defining the relevant timing parameters of the part not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). VDDQ DQ DQS Output DUT DQS ...

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... IS43DR32800A, IS43/46DR32801A t DQSH DQS DQS/ DQS DQS t WPRE V (ac (ac DMin Data Input (Write) Timing CK/CK CK DQS DQS/DQS DQS t RPRE DQ Data Output (Read) Timing 5. AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions. 6. All voltages are referenced to VSS. 7. These parameters guarantee device behavior, but they are not necessarily tested on each device They may be guaranteed by device design or tester correlation. ...

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... IS43DR32800A, IS43/46DR32801A 7. Timings are specified with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode. See Specific Notes on derating for other slew rate values. 8. Data setup and hold time derating (t DtDS, DtDH derating values for DDR2-400, DDR2-553 (All units in ‘ps’; the note applies to the entire table) 4.0 V/ns 3.0 V/ns DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DQ 2.0 125 ...

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... IS43DR32800A, IS43/46DR32801A DtDS1, DtDH1 derating values for DDR2-400, DDR2-533 (All units in ‘ps’; the note applies to the entire table) 2.0 V/ns 1.5 V/ns DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH1 DQ 2.0 188 167 145 125 Slew 1.5 146 167 125 125 rate 1.0 63 125 42 83 V/ns 0 ...

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... IS43DR32800A, IS43/46DR32801A 9. Input Setup and Hold Time Derating (tIS, tIH) tIS, tIH Derating Values for DDR2-400, DDR2-533 DtIS 4.0 187 3.5 179 3 167 2.5 150 2.0 125 1.5 83 1.0 0 0.9 -11 Command/ 0.8 -25 Address Slew rate 0.7 -43 (V/ns) 0.6 -67 0.5 -110 0.4 -175 0.3 -285 0.25 -350 0.2 -525 0.15 -800 0.1 -1450 For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the DtIS and DtIH derating value respectively. Example: tIS (total setup time) = tIS(base) + DtIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vih(ac)min ...

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... IS43DR32800A, IS43/46DR32801A 10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 11. MIN ( tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces. 12. tQH = tHP – tQHS, where minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH, tCL). tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits ...

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... IS43DR32800A, IS43/46DR32801A 20. Input waveform timing tDS with differential data strobe enabled is referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(dc)max and Vih(dc)min. 21. Input waveform timing tDH with differential data strobe enabled is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH(dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL(dc) level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(dc)max and Vih(dc)min. 22. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the device under test ...

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... IS43DR32800A, IS43/46DR32801A 33. tDAL [nCK [nCK] + tnRP [nCK {tRP [ps] / tCK(avg) [ps] }, where WR is the value programmed in the mode register set. 34. New units, ‘tCK(avg)’ and ‘nCK’, are introduced in DDR2-667 and DDR2-800. Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, ‘tCK’ is used for both concepts. ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2, even if (Tm tCK(avg) + tERR(2per),min ...

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... IS43DR32800A, IS43/46DR32801A 36. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and max of SPEC values are to be used for calculations in the table below.) Parameter Symbol Absolute clock period tCK(abs) Absolute clock HIGH tCH(abs) pulse width Absolute clock LOW tCL(abs) pulse width Example: For DDR2-667, tCH(abs),min = ( 0.48 x 3000 125 ps = 1315 ps 37. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter used in conjunction with tQHS to derive the DRAM output timing tQH. ...

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... IS43DR32800A, IS43/46DR32801A 41. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(per),min = - 72 ps and tJIT(per),max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),min = 0.9 x tCK(avg 2178 ps and tRPRE,max(derated) = tRPRE,max + tJIT(per),max = 1.1 x tCK(avg 2843 ps. (Caution on the min/max usage!) 42. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(duty) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(duty),min = - 72 ps and tJIT(duty),max = + 93 ps, then tRPST,min(derated) = tRPST,min + tJIT(duty),min = 0 ...

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... IS43DR32800A, IS43/46DR32801A FUNCTIONAL DESCRIPTION Power-up and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. For DDR2 SDRAMs, both bits BA0 and BA1 must be decoded for Mode/ Extended Mode Register Set (MRS/EMRS)commands. Users must initialize all four Mode Registers. The registers may be initialized in any order. Power-up and Initialization Sequence The following sequence is required for Power-up and Initialization. a) Either one of the following sequence is required for Power-up. a1) While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT LOW state (all other inputs may be undefined.) The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD min ...

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... IS43DR32800A, IS43/46DR32801A Power-up and Initialization Sequence (cont'd) f) Issue EMRS to enable DLL. g) Issue a Mode Register Set command for DLL reset. h) Issue a precharge all command. i) Issue 2 or more auto-refresh commands. j) Issue a MRS command with LOW initialize device operation. (i.e. to program operating parameters without resetting the DLL least 200 clocks after step h, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD calibration is not used, EMRS to EMR(1) to set OCD Calibration Default (A9=A8=A7=HIGH) followed by EMRS to EMR(1) to exit OCD Calibration Mode (A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1). l) The DDR2 SDRAM is now ready for normal operation. ...

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... IS43DR32800A, IS43/46DR32801A Mode Register (MR) The mode register stores the data for controlling the various operating modes of the DDR2 SDRAM. It controls CAS latency, burst length, burst sequence, DLL reset, WR and power down exit time to make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be programmed during initialization for proper operation. The mode register is written by asserting LOW on CS, RAS, CAS, WE, BA0 and BA1, while controlling the state of address pins A0 - A12. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state ...

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... IS43DR32800A, IS43/46DR32801A Burst mode operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. DDR2 SDRAM supports 4 bit burst and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst type, either sequential or interleaved, is programmable and defined by MR[A3], which is similar to the DDR SDRAM operation. Seamless burst read or write operations are supported. Unlike DDR devices, interruption of a burst read or write cycle during mode operation is prohibited ...

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... IS43DR32800A, IS43/46DR32801A Extended Mode Registers (EMR) Extended Mode Register 1 (EMR1) The EMR(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, ODT, DQS disable, OCD program, output buffer disable. The default value of the EMR(1) is not defined, therefore the EMR(1) must be programmed during initialization for proper operation. The EMR(1) is written by asserting LOW on CS, RAS, CAS, WE, HIGH on BA0 and LOW on BA1, while controlling the states of address pins A0 - A12. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the EMR(1) ...

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... IS43DR32800A, IS43/46DR32801A A12 0 Address Mode Field Register 1 BA1 0 BA0 1 *4 Qoff A12 A10 *1 0 A11 0 1 A10 DQS OCD A8 Program Rtt Additive 0 A4 Latency Rtt 1 A1 D.I DLL 1 EMR(1) Notes: 1. A11 is reserved for future use and must be set to 0 when programming the EMR(1). ...

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... IS43DR32800A, IS43/46DR32801A Extended Mode Register 2 (EMR2) The EMR(2) controls refresh related features. The default value of the EMR(2) is not defined, therefore the EMR(2) must be programmed during initialization for proper operation. The EMR(2) is written by asserting LOW on CS, RAS, CAS, WE, HIGH on BA1 and LOW on BA0, while controlling the states of address pins A0 - A11/A12. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the EMR(2). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the EMR(2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state ...

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... IS43DR32800A, IS43/46DR32801A TRUTh TABLES Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the speechified initialization sequence before normal operation can continue. Command Truth Table Function CKE Previous Current Cycle Cycle (Extended) Mode H H Register Set (Load Mode) Refresh (REF Self Refresh Entry H L Self Refresh Exit L H Single Bank H H Precharge Precharge all Banks ...

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... IS43DR32800A, IS43/46DR32801A Clock Enable (CKE) Truth Table Current  CKE State 2 Previous Cycle   Current Cycle 1 (N-1) Power Down L L Self Refresh L L Bank(s) H Active All Banks H Idle H H Notes: 1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. 3. COMMAND (N) is the command registered at clock edge N, and ACTION ( result of COMMAND (N). ...

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... IS43DR32800A, IS43/46DR32801A DESELECT The DESELECT function (CS HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. DESELECT is also referred to as COMMAND INHIBIT. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to perform a NOP (CS is LOW; RAS, CAS, and WE are HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Mode Register Set (MRS or EMRS) The mode registers are loaded via bank address and address inputs ...

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... IS43DR32800A, IS43/46DR32801A PREChARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation a specified time (tRP) after the PRECHARGE command is issued, except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. After a bank has been precharged the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle state the previously open row is already in the process of precharging ...

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... IS43DR32800A, IS43/46DR32801A ODT On/Off Timing for Active/Standby mode CKE (ac) ODT IH t AOND AON,min ODT On/Off Timing for Power-Down mode CKE ODT (ac AONPD,min t AONPD,max Integrated Silicon Solution, Inc. — www.issi.com Rev.  ...

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... IS43DR32800A, IS43/46DR32801A ORDERING INFORMATION - V   Standard Page Size: IS43DR32800A Commercial Range: Tc = 0 C to +85 o Clock (Mhz) Speed Grade CL-tRCD-tRP Order Part No. 266 DDR2-533C 200 DDR2-400B Industrial Range: Tc = -40 C to +95 o Clock (Mhz) Speed Grade CL-tRCD-tRP Order  ...

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... IS43DR32800A, IS43/46DR32801A Integrated Silicon Solution, Inc. — www.issi.com Rev.  00E 09/08/2010 7. Dimensions Package 41 ...