SN74LVCZ161284AGR Texas Instruments, SN74LVCZ161284AGR Datasheet

SN74LVCZ161284AGR
Manufacturer Part Number	SN74LVCZ161284AGR
Description	IC 19-BIT BUS INTERFACE 48-TSSOP
Manufacturer	Texas Instruments
Series	74LVCZ
SN74LVCZ161284AGR datasheets	1. SN74LVCZ161284AGR.pdf (13 pages)

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Specifications of SN74LVCZ161284AGR
Logic Type	IEEE STD 1284 Translation Transceiver	Supply Voltage	3 V ~ 3.6 V
Number Of Bits	19	Operating Temperature	0°C ~ 70°C
Mounting Type	Surface Mount	Package / Case	48-TSSOP
Lead Free Status / RoHS Status	Lead free / RoHS Compliant	Other names	296-12025-2

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FEATURES

Power-On Reset (POR) Prevents Printer

Errors When Printer Is Turned On, But No

Valid Signal Is at Pins A9–A13

Operates From 3 V to 3.6 V

1.4-k

Pullup Resistors Integrated on All

Open-Drain Outputs Eliminate the Need for

Discrete Resistors

Designed for IEEE Std 1284-I (Level-1 Type)

and IEEE Std 1284-II (Level-2 Type) Electrical

Specifications

Flow-Through Architecture Optimizes PCB

Layout

and Power-Up 3-State Support Hot

off

Insertion

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

– 4000-V Human-Body Model (A114-A)

– 350-V Machine Model (A115-A)

– 1500-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

The SN74LVCZ161284A is designed for 3-V to 3.6-V

operation. This device provides asynchronous

two-way communication between data buses. The

control-function implementation minimizes external

timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control (DIR) input

is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side and

four receivers. The SN74LVCZ161284A has one receiver dedicated to the HOST LOGIC line and a driver to

drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a

totem-pole configuration and in an open-drain configuration when HD is low. This meets the drive requirements

as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface

specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have

a 1.4-k

integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low

state or if the output voltage is above V

The device has two supply voltages. V

and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even

when V

CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

PACKAGE

0°C to 70°C

TSSOP – DGG

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER

PERI LOGIC IN

HOST LOGIC OUT

CABLE. If V

CABLE is off, PERI LOGIC OUT is set to low.

is designed for 3-V to 3.6-V operation. V

ORDERING INFORMATION

(1)

ORDERABLE PART NUMBER

Tape and reel

SN74LVCZ161284AGR

SN74LVCZ161284A

WITH ERROR-FREE POWER UP

SCES358B – SEPTEMBER 2001 – REVISED MAY 2005

DGG PACKAGE

(TOP VIEW)

DIR

A10

Y10

A11

Y11

A12

Y12

A13

Y13

CABLE

GND

CABLE

PERI LOGIC OUT

A14

C14

A15

C15

A16

C16

A17

C17

HOST LOGIC IN

CABLE supplies the inputs

TOP-SIDE MARKING

LVCZ161284A

Download datasheet (315Kb)

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SN74LVCZ161284AGR Summary of contents
Page 1 ... HOST LOGIC OUT CABLE CABLE is off, PERI LOGIC OUT is set to low designed for 3-V to 3.6-V operation ORDERING INFORMATION (1) ORDERABLE PART NUMBER Tape and reel SN74LVCZ161284AGR SN74LVCZ161284A WITH ERROR-FREE POWER UP SCES358B – SEPTEMBER 2001 – REVISED MAY 2005 DGG PACKAGE (TOP VIEW DIR A9 ... Page 2 SN74LVCZ161284A 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP SCES358B – SEPTEMBER 2001 – REVISED MAY 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) The power-on reset (POR) ensures that the Y outputs (Y9–Y13) stay in the high state after power on ... Page 3 V CABLE CC 48 DIR 1 HD A1–A8 A9–A13 See Note C 19 PERI LOGIC IN A14–A17 24 HOST LOGIC OUT NOTES: A. The PMOS transistors prevent backdriving current from the signal pins to V PMOS transistor is ... Page 4 SN74LVCZ161284A 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP SCES358B – SEPTEMBER 2001 – REVISED MAY 2005 (1) Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) V CABLE Supply voltage range CC V Supply voltage ... Page 5 Electrical Characteristics over recommended operating free-air temperature range, V PARAMETER All inputs except V C inputs and HOST LOGIC IN t Hysteresis HOST LOGIC IN (V – T– C inputs HD high, B and Y outputs ... Page 6 SN74LVCZ161284A 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP SCES358B – SEPTEMBER 2001 – REVISED MAY 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 3) PARAMETER t PLH ... Page 7 PARAMETER MEASUREMENT INFORMATION V CABLE CC 62 TP1 Sink Load From Output Under Test Source Load 62 SLEW RATE A-TO-B OR A-TO-Y LOAD (TOTEM POLE) V CABLE CC TP1 500 From Output C ... Page 8 SN74LVCZ161284A 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP SCES358B – SEPTEMBER 2001 – REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION 500 From Output Under Test 500 (see Note A) LOAD CIRCUIT Input (see ... Page 9 ... PACKAGING INFORMATION (1) Orderable Device Status 74LVCZ161284AGRG4 ACTIVE SN74LVCZ161284AGR ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design ... Page 10 ... TAPE AND REEL INFORMATION All dimensions are nominal Device Package Package Type Drawing SN74LVCZ161284AGR TSSOP DGG PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 (mm) Diameter Width (mm) W1 (mm) 48 2000 330.0 24.4 8.6 Pack Materials-Page 1 16-Apr-2008 B0 (mm) K0 (mm Pin1 (mm) (mm) Quadrant 15 ... Page 11 ... Device Package Type SN74LVCZ161284AGR TSSOP PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) DGG 48 2000 Pack Materials-Page 2 16-Apr-2008 Width (mm) Height (mm) 346.0 346.0 41.0 ... Page 12 DGG (R-PDSO-G*) 48 PINS SHOWN 0, 1,20 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. ... Page 13 ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...

SN74LVCZ161284AGR Summary of contents

Page 1
... HOST LOGIC OUT CABLE CABLE is off, PERI LOGIC OUT is set to low designed for 3-V to 3.6-V operation ORDERING INFORMATION (1) ORDERABLE PART NUMBER Tape and reel SN74LVCZ161284AGR SN74LVCZ161284A WITH ERROR-FREE POWER UP SCES358B – SEPTEMBER 2001 – REVISED MAY 2005 DGG PACKAGE (TOP VIEW DIR A9 ...
Page 2
SN74LVCZ161284A 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP SCES358B – SEPTEMBER 2001 – REVISED MAY 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) The power-on reset (POR) ensures that the Y outputs (Y9–Y13) stay in the high state after power on ...
Page 3
V CABLE CC 48 DIR 1 HD A1–A8 A9–A13 See Note C 19 PERI LOGIC IN A14–A17 24 HOST LOGIC OUT NOTES: A. The PMOS transistors prevent backdriving current from the signal pins to V PMOS transistor is ...
Page 4
SN74LVCZ161284A 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP SCES358B – SEPTEMBER 2001 – REVISED MAY 2005 (1) Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) V CABLE Supply voltage range CC V Supply voltage ...
Page 5
Electrical Characteristics over recommended operating free-air temperature range, V PARAMETER All inputs except V C inputs and HOST LOGIC IN t Hysteresis HOST LOGIC IN (V – T– C inputs HD high, B and Y outputs ...
Page 6
SN74LVCZ161284A 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP SCES358B – SEPTEMBER 2001 – REVISED MAY 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 3) PARAMETER t PLH ...
Page 7
PARAMETER MEASUREMENT INFORMATION V CABLE CC 62 TP1 Sink Load From Output Under Test Source Load 62 SLEW RATE A-TO-B OR A-TO-Y LOAD (TOTEM POLE) V CABLE CC TP1 500 From Output C ...
Page 8
SN74LVCZ161284A 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP SCES358B – SEPTEMBER 2001 – REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION 500 From Output Under Test 500 (see Note A) LOAD CIRCUIT Input (see ...
Page 9
... PACKAGING INFORMATION (1) Orderable Device Status 74LVCZ161284AGRG4 ACTIVE SN74LVCZ161284AGR ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design ...
Page 10
... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing SN74LVCZ161284AGR TSSOP DGG PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 (mm) Diameter Width (mm) W1 (mm) 48 2000 330.0 24.4 8.6 Pack Materials-Page 1 16-Apr-2008 B0 (mm) K0 (mm Pin1 (mm) (mm) Quadrant 15 ...
Page 11
... Device Package Type SN74LVCZ161284AGR TSSOP PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) DGG 48 2000 Pack Materials-Page 2 16-Apr-2008 Width (mm) Height (mm) 346.0 346.0 41.0 ...
Page 12
DGG (R-PDSO-G**) 48 PINS SHOWN 0, 1,20 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. ...
Page 13
... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...