VCBUP8168CCYG2

Manufacturer Part NumberVCBUP8168CCYG2
DescriptionDigital Signal Processors & Controllers - DSP, DSC DaVinci Digital Media Processor
ManufacturerTexas Instruments
SeriesTMS320DM8168
VCBUP8168CCYG2 datasheet
 


Specifications of VCBUP8168CCYG2

RohsyesCoreTMS320DM816x
Data Bus Width32 bitProgram Memory Size32 KB
Data Ram Size256 KBMaximum Clock Frequency1.35 GHz
Number Of Programmable I/os64Number Of Timers7
Device Million Instructions Per Second9000 MIPsOperating Supply Voltage1.5 V, 1.8 V, 3.3 V
Maximum Operating Temperature+ 95 CPackage / CaseFCBGA-1031
Mounting StyleSMD/SMTInstruction Set ArchitectureFloating Point
Interface TypeSPIMinimum Operating Temperature0 C
On-chip AdcNoProcessor SeriesTMS320DM8168
ProductDSPsProgram Memory TypeCache
Supply Current3.3 VSupply Voltage - Min1.5 V
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TMS320DM816x DaVinci Video Processors
Check for Samples: TMS320DM8168, TMS320DM8167, TMS320DM8166,
1 Device Summary
1.1
Features
1234567891011
• High-Performance DaVinci™ Video Processors
®
– ARM
Cortex™-A8 RISC Processor
Up to 1.35 GHz
– C674x VLIW DSP
Up to 1.125 GHz
Up to 9000 MIPS and 6750 MFLOPS
Fully Software-Compatible with C67x+™
and C64x+™
®
• ARM
Cortex™-A8 Core
– ARMv7 Architecture
In-Order, Dual-Issue, Superscalar
Processor Core
NEON™ Multimedia Architecture
– Supports Integer and Floating Point (VFPv3-
IEEE754 compliant)
®
Jazelle
RCT Execution Environment
®
• ARM
Cortex™-A8 Memory Architecture
– 32K-Byte Instruction and Data Caches
– 256K-Byte L2 Cache
– 64K-Byte RAM, 48K-Byte Boot ROM
• TMS320C674x Floating-Point VLIW DSP
– 64 General-Purpose Registers (32-Bit)
– Six ALU (32-Bit and 40-Bit) Functional Units
Supports 32-Bit Integer, SP (IEEE Single
Precision, 32-Bit) and DP (IEEE Double
Precision, 64-Bit) Floating Point
Supports up to Four SP Adds Per Clock
and Four DP Adds Every Two Clocks
Supports up to Two Floating-Point (SP or
DP) Approximate Reciprocal or Square
Root Operations Per Cycle
– Two Multiply Functional Units
Mixed-Precision IEEE Floating-Point
Multiply Supported up to:
– 2 SP x SP → SP Per Clock
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DaVinci, C64x+, SmartReflex, TMS320C6000, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas
2
Instruments.
Cortex, NEON are trademarks of ARM Ltd or its subsidiaries.
3
ARM, Jazelle, Thumb are registered trademarks of ARM Ltd or its subsidiaries.
4
USSE, POWERVR are trademarks of Imagination Technologies Limited.
5
OpenVG, OpenMax are trademarks of Khronos Group Inc.
6
Direct3D, Microsoft, Windows are registered trademarks of Microsoft Corporation in the United States and/or other countries.
7
2
I
C BUS is a registered trademark of NXP B.V. Corporation Netherlands.
8
PCI Express, PCIe are registered trademarks of PCI-SIG.
9
OpenGL is a registered trademark of Silicon Graphics International Corp. or its subsidiaries in the United States and/or other
10
countries.
All other trademarks are the property of their respective owners.
11
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
TMS320DM8165
– 2 SP x SP → DP Every Two Clocks
– 2 SP x DP → DP Every Three Clocks
– 2 DP x DP → DP Every Four Clocks
Fixed-Point Multiply Supports Two 32 x
32 Multiplies, Four 16 x 16-bit Multiplies
including Complex Multiplies, or Eight 8 x
8-Bit Multiplies per Clock Cycle
• C674x Two-Level Memory Architecture
– 32K-Byte L1P and L1D RAM and Cache
– 256K-Byte L2 Unified Mapped RAM and
Caches
• System Memory Management Unit (System
MMU)
– Maps C674x DSP and EMDA TCB Memory
Accesses to System Addresses
• 512K-Bytes On-Chip Memory Controller
(OCMC) RAM
• Media Controller
– Manages HDVPSS and HDVICP2 modules
• Up to Three Programmable High-Definition
Video Image Coprocessing (HDVICP2) Engines
– Encode, Decode, Transcode Operations
– H.264, MPEG2, VC1, MPEG4 SP and ASP
• SGX530 3D Graphics Engine (available only on
the DM8168 and DM8166 device)
– Delivers up to 30 MTriangles per second
– Universal Scalable Shader Engine
®
– Direct3D
Mobile, OpenGL
OpenVG™ 1.1, OpenMax™ API Support
– Advanced Geometry DMA Driven Operation
– Programmable HQ Image Anti-Aliasing
• Endianness
– ARM, DSP Instructions and Data – Little
Endian
• HD Video Processing Subsystem (HDVPSS)
Copyright © 2011–2013, Texas Instruments Incorporated
®
ES 1.1 and 2.0,

VCBUP8168CCYG2 Summary of contents

  • Page 1

    ... → SP Per Clock 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DaVinci, C64x+, SmartReflex, TMS320C6000, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas 2 Instruments ...

  • Page 2

    ... Design Rules • 40-nm CMOS Technology • 3.3-V Single-Ended LVCMOS IOs (except for DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN at 1.8 V) Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com 2 ® C BUS ) Ports ® ROM Bootloader (RBL) Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 3

    ... ARM and DSP which include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Microsoft interface for visibility into source code execution. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: ® Cortex™-A8 RISC CPU with NEON™ extension, TI C674x VLIW ® ...

  • Page 4

    ... PCB costs. It also allows PCB routing in only two signal layers due to the increased layer efficiency of the Via Channel™ BGA technology. 4 Device Summary Product Folder Links: Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 5

    ... B. Three HD Video Image Coprocessors (HDVICP2) are available on the TMS320DM8168 and TMS320DM8167 devices; two (HDVICP2-0 and HDVICP2-1) are available on the TMS320DM8166 and TMS320DM8165 devices. Figure 1-1. TMS320DM816x Functional Block Diagram Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DSP Subsystem C674x ...

  • Page 6

    ... Copyright © 2011–2013, Texas Instruments Incorporated 141 144 149 160 172 172 173 174 210 214 220 229 232 253 262 269 273 ...

  • Page 7

    ... LOCATION System Table 5-2 Interconnect Power, Reset, Table 7-4 Clocking, and Interrupts Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Revision History DM816x Revisions ADDITIONS, MODIFICATIONS, DELETIONS Modified C674x CONFIG for Timers 4-6 Changed Parameter NO. 1 MIN value Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 ...

  • Page 8

    ... Device Overview Product Folder Links: Table 2-1. For more detailed information on the Section 2.2, Device Characteristics. Table 2-1. Device Comparison DEVICES TMS320DM8168 TMS320DM8167 TMS320DM8166 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com TMS320DM8165 Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 9

    ... Serial ATA (SATA) RTC GPIO On-Chip Memory Organization Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Asynchronous (8-bit and 16-bit bus width) RAM, NOR, 2 (Supports High-Speed and Full-Speed as a Device and High-Speed, Full-Speed, and Low-Speed (with SIR, MIR, CIR support and RTS and CTS flow ...

  • Page 10

    ... ARM Cortex-A8: 1200 MHz DSP: 1000 MHz ARM Cortex-A8: 1350 MHz DSP: 1125 MHz ARM Cortex-A8: 1.00 ns DSP: 1.25 ns ARM Cortex-A8: 0.83 ns DSP: 1.00 ns ARM Cortex-A8: 0.74 ns DSP: 0.89 ns 1.0 V with Required AVS Capability 0.9 V 1.0 V 1.5 V, 1.8 V, 3.3 V 1031-Pin BGA (CYG) 0.04 µm PD Table 9-1. Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 11

    ... The ARM Cortex-A8 trace port is connected to the system-level embedded trace buffer (ETB). The ETB has a 32KB buffer memory. ETB enabled debug tools are required to read and interpret the captured trace data. For more details on the ETB, see Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: L3 DMM ...

  • Page 12

    ... DMM port. The DMM port is 128-bits wide and provides the ARM Cortex-A8 direct access to the DDR memories, while the L3 interconnect port is 64-bits wide and provides access to the remaining device modules. 12 Device Overview Product Folder Links: 7.4. Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 13

    ... Bandwidth Mgmt Memory Protect L1D Cache Control 32K Bytes L1D RAM and Cache Figure 2-2. C674x Megamodule Block Diagram Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: 256K Bytes L2 RAM with ECC 256 256 Cache Control Memory Protect Bandwidth Mgmt ...

  • Page 14

    ... Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions. 14 Device Overview Product Folder Links: Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 15

    ... TMS320C674x DSP CPU and Instruction Set User's Guide (literature number SPRUFE8) • TMS320C674x DSP Megamodule Reference Guide (literature number SPRUFK5) Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 TMS320DM8168, TMS320DM8167 TMS320DM8166, TMS320DM8165 SPRS614D – ...

  • Page 16

    ... A file A (A0, A2, (A1, A3, A4...A30) A5...A31) (D) (D) (A) (B) ( Even register Odd file B register (B0, B2, file B B4...B30) (B1, B3, B5...B31) (C) (B) (A) (D) (D) Control Register is 64 bits. dst connects to even register files Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 17

    ... MMU_FLUSH_ENTRY 0x4801 0068h 0x4801 006Ch 0x4801 0070h MMU_EMU_FAULT_AD 0x4801 0080h Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: ACRONYM REGISTER NAME MMU_REVISION Revision Configuration Status IRQ Status IRQ Enable Table Walking Logic ...

  • Page 18

    ... Interrupt signaling is used to notify the receiver that a message has been queued or to notify the sender about an overflow situation. The Mailbox module supports the following features (see • 12 mailboxes 18 Device Overview Product Folder Links: Figure 2-4): Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 19

    ... MAILBOX_IRQSTATUS_CLR_u 0x480C 8108 + (0x10 * u) MAILBOX_IRQENABLE_SET_u 0x480C 810C + (0x10 * u) MAILBOX_IRQENABLE_CLR_u 0x480C 8140 (1) For the range of m and u, see Table 2-4. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Mailbox Mailbox Mailbox Mailbox Mailbox Mailbox Interrupt Interrupt C674x+ DSP Table 2-4 ...

  • Page 20

    ... Table 2-25 provide SIZE SEE 256 Bytes Table 2-8 256 Bytes Table 2-9 256 Bytes Table 2-11 256 Bytes Table 2-12 256 Bytes Table 2-13 256 Bytes Table 2-14 256 Bytes Table 2-15 256 Bytes Table 2-16 256 Bytes Table 2-17 256 Bytes Table 2-18 Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 21

    ... Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: MODULE NAME PRM_DEFAULT PRM_IVAHD0 PRM_IVAHD1 PRM_IVAHD2 PRM_SGX CM_ALWON PRM_ALWON ACRONYM ...

  • Page 22

    ... USB clock management control SATA clock management control PCI clock management control ACRONYM REGISTER NAME HDVICP2-0 clock domain power state transition HDVICP2-0 SL2 clock management control Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 23

    ... PM_IVAHD1_PWRSTCTRL 0x4818 0D04 PM_IVAHD1_PWRSTST 0x4818 0D10 RM_IVAHD1_RSTCTRL 0x4818 0D14 RM_IVAHD1_RSTST Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: ACRONYM REGISTER NAME HDVICP2-1 clock domain power state transition HDVICP2-1 SL2 clock management control ACRONYM REGISTER NAME HDVICP2-2 clock domain power state transition HDVICP2-2 SL2 clock management control Table 2-17 ...

  • Page 24

    ... Timer3 clock management control Timer4 clock management control Timer5 clock management control Timer6 clock management control Timer7 clock management control WDTIMER clock management control SPI clock management control Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 25

    ... CM_ALWON_CUST_EFUSE_CLKCTRL Table 2-25. PRM_ALWON Register Summary HEX ADDRESS 0x4818 1810 RM_ALWON_RSTCTRL 0x4818 1814 RM_ALWON_RSTST Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: ACRONYM REGISTER NAME MAILBOX clock management control SPINBOX clock management control MMU DATA clock management control MMU CFG clock management control ...

  • Page 26

    ... Advanced and standard 2D operations [for example, vector graphics, block level transfers (BLTs), raster operations (ROPs)]. 26 Device Overview Product Folder Links: ® VS3.0, PS3.0, and OpenGL 2.0. Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 27

    ... Q1 Reserved 0x4100 0000 Q1 Reserved 0x4200 0000 Q1 L3 CFG Regs 0x4400 0000 Q1 Reserved 0x44C0 0000 Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 2-26. L3 Memory Map END ADDRESS SIZE (HEX) (HEX) 0x1FFF FFFF 496MB 0x2FFF FFFF 256MB 0x3FFF FFFF 256MB ...

  • Page 28

    ... Configuration registers Configuration registers Reserved HDVICP2-2 Host Port HDVICP2-2 SL2 Port Reserved SGX530 Slave Port Reserved Reserved HDVICP2-0 Host Port HDVICP2-0 SL2 Port HDVICP2-1 Host Port HDVICP2-1 SL2 Port Reserved Reserved Virtual Tiled Address Space Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 29

    ... DMM control registers. (4) DDR EMIF0 and DDR EMIF1 addresses may be contiguous or bank interleaved depending on configuration of the DDR DMM; for more details, see the DDR DMM documentation. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 2-26. L3 Memory Map (continued) END ADDRESS ...

  • Page 30

    ... Support Registers Reserved Peripheral Registers Support Registers Peripheral Registers Support Registers Peripheral Registers Support Registers Reserved Peripheral Registers Support Registers Reserved Peripheral Registers Support Registers Reserved Peripheral Registers Support Registers Peripheral Registers Support Registers Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 31

    ... Reserved 0x4818 4000 SmartReflex0 0x4818 8000 0x4818 9000 SmartReflex1 0x4818 A000 0x4818 B000 Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: END ADDRESS (HEX) SIZE 0x4804 4FFF 4KB 0x4804 5FFF 4KB 0x4804 6FFF 4KB 0x4804 7FFF ...

  • Page 32

    ... Reserved Reserved Reserved Reserved Peripheral Registers Support Registers Peripheral Registers Support Registers Reserved Cortex™-A8 Accessible Only Cortex™-A8 Accessible Only Cortex™-A8 Accessible Only Cortex™-A8 Accessible Only Cortex™-A8 Accessible Only Reserved Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 33

    ... SATA 0x4A14 0000 0x4A15 0000 Reserved 0x4A15 1000 Reserved 0x4A18 0000 0x4A1A 0000 Reserved 0x4A1A 1000 Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 2-28. END ADDRESS (HEX) SIZE 0x4A00 07FF 2KB 0x4A00 0FFF 2KB 0x4A00 13FF ...

  • Page 34

    ... DESCRIPTION Natural 0° View 0° with Vertical Mirror View 0° with Horizontal Mirror View 180° View 90° with Vertical Mirror View 270° View 90° View 90° with Horizontal Mirror View Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 35

    ... ARM Subsystem 0x4820 0000 (1) INTC (1) Reserved 0x4820 1000 (1) Reserved 0x4824 1000 Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 2-30. Cortex™-A8 Memory Map END ADDRESS (HEX) SIZE 0x000F FFFF 1MB 0x1FFF FFFF 512MB 0x2FFF FFFF 256MB ...

  • Page 36

    ... HDVICP2-2 SL2 Port Reserved SGX530 Slave Port (DM8168 and DM8166 only) Reserved (DM8167 and DM8165 only) Reserved HDVICP2-0 Host Port HDVICP2-0 SL2 Port HDVICP2-1 Host Port HDVICP2-1 SL2 Port Reserved TILER Window DDR DDR Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 37

    ... Addresses 0x1000 0000 to 0x10FF FFFF are mapped to C674x internal addresses 0x0000 0000 to 0x00FF FFFF. (5) These accesses are routed through the System MMU where the page tables translate to the physical L3 addresses shown in 26. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 2-31. C674x Memory Map ...

  • Page 38

    ... Pin map sections and L show the different pin names for silicon revision 1.x devices and silicon revision 2.x devices. 38 Device Pins Product Folder Links: show the bottom view of the package pin assignments in 15 sections (A, NOTE Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 39

    ... DDR[0]_DQS[0] E DDR[0]_D[4] D VSS DDR[0]_D[7] DDR[0]_DQM[ DDR[0]_D[0] DDR[0]_D[5] DDR[0]_D[15] DVDD_DDR[0] DDR[0]_D[14] A VSS Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SD_SDWP/ GPMC_A[15]/ VSS VSS GP1[8] VSS VSS VSS UART0_DSR/ UART0_DCD/ UART0_DTR/ GPMC_A[19]/ GPMC_A[18]/ GPMC_A[20]/ GPMC_A[24]/ GPMC_A[23]/ GPMC_A[12]/ ...

  • Page 40

    ... CVDDC CVDD CVDDC CVDD DDR[0]_BA[2] DDR[0]_A[12] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] VSS VSS VSS VSS VSS VSS DDR[0]_A[2] VSS DDR[0]_CLK[1] DDR[0]_A[13] DDR[0]_CLK[1] DDR[0]_ODT[ Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 41

    ... DDR[0]_RST D DDR[0]_CKE DEV_MXO C VSS VDDA_PLL B DDR[0]_CS[0] DEVOSC_VSS DEV_MXI/ VREFSSTL_DDR[0] VDDA_PLL A DEV_CLKIN Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: CVDD CVDD CVDD CVDD CVDD CVDD DDR[1]_A[1] DDR[1]_A[12] RSV4 DVDD_DDR[1] DVDD_DDR[1] DVDD_DDR[1] DVDD_DDR[1] DVDD_DDR[1] DVDD_DDR[1] DVDD_DDR[1] ...

  • Page 42

    ... VSS VSS VSS RSV19 I2C[0]_SCL TMS GP0[0] GP1[30]/ GP0[3]/ SATA_ACT0_LED TCLKIN GP0[4] VSS VSS VSS DDR[1]_D[23] DDR[1]_D[9] DDR[1]_D[11] DDR[1]_D[10] DDR[1]_D[19] DDR[1]_D[13] DDR[1]_D[17] DDR[1]_VTP 31 32 Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 43

    ... DDR[1]_CAS DDR[1]_D[29] C DDR[1]_A[11] DDR[1]_CLK[0] DDR[1]_D[25] B DDR[1]_A[0] DVDD_DDR[1] A DDR[1]_CLK[ Figure 3-5. Pin Map [Section D] - Silicon Revision 2.x Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DVDD_3P3 VDD_USB0_3P3 VDD_USB1_3P3 DVDD_3P3 DVDD_3P3 DVDD_3P3 RSV10 RSV11 TDO GP0[1] DVDD_3P3 GP0[2] DDR[1]_D[18] DDR[1]_D[28] ...

  • Page 44

    ... DDR[1]_DQM[0] DDR[1]_D[7] DDR[1]_D[15] DDR[1]_D[5] DDR[1]_D[0] DDR[1]_D[14] DVDD_DDR[ Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com EMU4 EMU2 VSS TCLK CLKIN32 RSTOUT POR VSS VSS 37 Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 45

    ... DDR[1]_DQS[ DDR[1]_D[8] C DDR[1]_DQM[1] DDR[1]_DQS[1] B DDR[1]_D[12] A DDR[1]_DQS[1] 33 Figure 3-7. Pin Map [Section E] - Silicon Revision 2.x Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: USB1_DRVVBUS USB1_DN USB1_DP RSV16 USB0_DN USB0_DP RSV17 USB0_DRVVBUS I2C[1]_SCL I2C[1]_SDA USB0_R1 VDD_USB0_VBUS ...

  • Page 46

    ... VOUT[1]_Y_YC[5]/ VIN[1]A_D[3] GPMC_CS[0] RSV44 VSS GPMC_DIR/ GPMC_WAIT GP1[20] GPMC_A[6]/ GP0[14]/ VSS CS0MUX[0] VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 7 8 Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 47

    ... GPMC_D[13] V VSS U DVDD_3P3 DVDD_3P3 DVDD_3P3 DVDD_3P3 DVDD_3P3 DVDD_3P3 Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: VOUT[0]_B_CB_C[5] VOUT[0]_B_CB_C[6] DVDD_3P3 DVDD_3P3 VOUT[0]_B_CB_C[8] VOUT[0]_R_CR[4]/ DVDD_3P3 VSS VOUT[0]_FLD/ VOUT[1]_Y_YC[4] _CLE CVDDC VOUT[0]_G_Y_YC[6] VOUT[0]_G_Y_YC[2] ...

  • Page 48

    ... VSS VSS DVDD1P8 RSV56 RSV55 RSV15 RSV54 RSV13 HDMI_HPDET RSV7 CVDDC CVDDC CVDDC CVDDC CVDD CVDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CVDD CVDD 23 24 Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 49

    ... Y VDDR_PCIE W VDDR_SATA V VSS U VDDR_SATA VDD_USB1_1P8 T RSV6 Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: MCA[0]_ACLKR MCA[0]_ACLKX MCA[0]_AHCLKX EMAC[0]_TXD[4] MCA[0]_AFSR VSS DVDD_3P3 DVDD_3P3 EMAC[0]_TXD[3] EMAC[0]_TXD[2] EMAC[0]_TXD[1] DVDD_3P3 DVDD_3P3 VSS DVDD_3P3 DVDD_3P3 ...

  • Page 50

    ... VSS SATA_RXP1 VDDT_SATA SATA_RXN1 SATA_RXP0 SATA_RXN0 VDD_USB1_VBUS VSS VSS Figure 3-12. Pin Map [Section J] Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com MCB_DR VSS VSS USB1_R1 37 Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 51

    ... RSV29 VSS VIN[1]A_D[14] AL RSV32 RSV30 Figure 3-14. Pin Map [Section K] - Silicon Revision 2.x Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: VIN[0]A_D[21]/ VOUT[1]_Y_YC[4]/ VIN[0]A_HSYNC VIN[1]A_D[2] VIN[0]B_FLD VIN[0]A_D[16]/ VOUT[1]_Y_YC[8]/ VOUT[1]_AVID/ VIN[1]A_HSYNC/ ...

  • Page 52

    ... VIN[0]A_D[10] VSS VSS VSS VSS VSS VSS VSS VIN[0]A_D[14] VIN[0]A_D[12] VIN[0]A_D[13] VIN[0]A_D[10] VSS VSS VSS VSS VSS VSS VSS 15 16 Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 53

    ... VIN[0]A_D[8] VIN[0]A_D[6] AP VDAC_RBIAS_SD AN RSV21 RSV22 AM VSS VSS VSS AL VSS VSS VSS Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: VSSA_REF_1P8 IOUTG RSV41 VDDA_REF_1P8 IOUTF IOUTA IOUTD IOUTB IOUTC VSSA_SD RSV61 VSSA_SD RSV60 RSV59 VSSA_SD VSSA_HD RSV58 ...

  • Page 54

    ... EMAC[1]_TXD[7] RSV33 RSV34 RSV35 Figure 3-18. Pin Map [Section N] Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com EMAC[1]_TXD[1] EMAC[1]_CRS VSS VSS VSS 31 32 Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 55

    ... EMAC[1]_RXDV EMAC1_RXD[3] AT EMAC[1]_RXD[ MCA[2]_AHCLKR/ AM MCA[2]_ACLKR/ MCA[1]_AXR[ Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: EMAC1_RXD[1] EMAC1_RXD[0] EMAC[1]_RXCLK MCA[2]_AXR[1]/ MCA[2]_AXR[0] MCA[2]_AMUTE MCA[2]_AFSX/ MCA[2]_AHCLKX/ MCB_CLKS/ DVDD_3P3 MCB_CLKR MCB_FSX ...

  • Page 56

    ... GPMC, GP0 DRIVE PINCTRL230 The CS0WAIT pin is also used by the ROM DVDD_3P3 bootloader to set up the size of BAR ranges in PCIe boot mode. Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Table 4-6. (4) (4) (4) Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 57

    ... DDR[0]_BA[1] B14 O DDR[0]_BA[0] F13 O ( Input Output High impedance Supply voltage, GND = Ground Analog signal. (2) Specifies the operating IO supply voltage for each signal. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) OTHER DVDD_DDR[0] DDR[0] Clock 0 DVDD_DDR[0] ...

  • Page 58

    ... DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DDR[0] Data Bus DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 59

    ... DDR[0]_D[ DDR[0]_D[ DDR[0]_D[ DDR[0]_D[ DDR[0]_D[ DDR[0]_VTP A6 I Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) OTHER DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DDR[0] Data Bus DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] ...

  • Page 60

    ... DVDD_DDR[1] DDR[1] On-Die Termination for Chip Select 0. O DVDD_DDR[1] DDR[1] On-Die Termination for Chip Select 1. O DVDD_DDR[1] DDR[1] Reset output O DVDD_DDR[1] O DVDD_DDR[1] DDR[1] Bank Address outputs O DVDD_DDR[1] Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 61

    ... DDR[1]_D[25] B27 DDR[1]_D[24] E29 DDR[1]_D[23] E31 DDR[1]_D[22] F29 DDR[1]_D[21] D30 DDR[1]_D[20] F30 DDR[1]_D[19] B31 DDR[1]_D[18] H28 DDR[1]_D[17] A31 DDR[1]_D[16] C30 Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) OTHER O DVDD_DDR[1] O DVDD_DDR[1] O DVDD_DDR[1] O DVDD_DDR[1] O DVDD_DDR[1] O DVDD_DDR[1] O DVDD_DDR[1] O DVDD_DDR[1] DDR[1] Address Bus ...

  • Page 62

    ... DVDD_DDR[1] IO DVDD_DDR[1] IO DVDD_DDR[1] IO DVDD_DDR[1] IO DVDD_DDR[1] IO DVDD_DDR[1] IO DVDD_DDR[1] DDR[1] Data Bus IO DVDD_DDR[1] IO DVDD_DDR[1] IO DVDD_DDR[1] IO DVDD_DDR[1] IO DVDD_DDR[1] IO DVDD_DDR[1] IO DVDD_DDR[1] IO DVDD_DDR[1] I DVDD_DDR[1] DDR VTP Compensation Resistor Connection Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 63

    ... For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 4.3.1, Pullup and Pulldown Resistors. (3) Specifies the operating IO supply voltage for each signal. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 3-4. EMAC Terminal Functions (1) (2) (3) ...

  • Page 64

    ... PULL: IPD / IPD - DRIVE [G]MII Receive Data Valid input PINCTRL60 DVDD_3P3 PULL: IPD / DIS - DRIVE [G]MII Receive Data Error input PINCTRL74 DVDD_3P3 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 65

    ... AU31 O EMAC[1]_TXD[3] AU32 EMAC[1]_TXD[2] AT32 EMAC[1]_TXD[1] AR32 EMAC[1]_TXD[0] AP31 EMAC[1]_TXEN AU30 O Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) (3) OTHER MUXED PULL: IPD / DIS - DRIVE [G]MII Transmit Clock input PINCTRL71 DVDD_3P3 - PINCTRL69 ...

  • Page 66

    ... PULL: IPD / DIS GPMC DRIVE General-Purpose Input/Output (IO) 0 [GP0] pin 19. PINCTRL232 DVDD_3P3 PULL: IPD / DIS GPMC DRIVE General-Purpose Input/Output (IO) 0 [GP0] pin 18. PINCTRL231 DVDD_3P3 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 67

    ... GP0[3]/ J31 IO TCLKIN GP0[2] K30 IO GP0[1] L29 IO GP0[0] K31 IO Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) (3) OTHER MUXED PULL: IPU / DIS GPMC, BOOT DRIVE General-Purpose Input/Output (IO) 0 [GP0] pin 17. PINCTRL230 DVDD_3P3 PULL: IPU / DIS GPMC, BOOT DRIVE General-Purpose Input/Output (IO) 0 [GP0] pin 16 ...

  • Page 68

    ... UART0, GPMC DRIVE General-Purpose Input/Output (IO) 1 [GP1] pin 18. PINCTRL179 DVDD_3P3 PULL: IPU / IPU UART0, GPMC DRIVE General-Purpose Input/Output (IO) 1 [GP1] pin 17. PINCTRL178 DVDD_3P3 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 69

    ... U3 IO GP1[2] SD_CLK/ GPMC_A[13 GP1[1] SD_POW/ GPMC_A[14 GP1[0] Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) (3) OTHER MUXED PULL: IPU / DIS UART0, GPMC DRIVE General-Purpose Input/Output (IO) 1 [GP1] pin 16. PINCTRL177 DVDD_3P3 PULL: IPD / DIS GPMC DRIVE General-Purpose Input/Output (IO) 1 [GP1] pin 15 ...

  • Page 70

    ... GPMC Direction Control for External Transceivers PINCTRL218 DVDD_3P3 PULL: IPU / IPD - DRIVE GPMC Write Protect output PINCTRL219 DVDD_3P3 PULL: IPD / IPD - DRIVE GPMC Wait input PINCTRL220 DVDD_3P3 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 71

    ... GPMC_A[23] SPI_SCS[1 GPMC_A[23] UART0_DCD/ GPMC_A[18 GPMC_A[23]/ GP1[18] GPMC_A[23 GP1[14] Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) (3) OTHER MUXED PULL: IPD / DIS GP0 DRIVE PINCTRL233 DVDD_3P3 GPMC Address 27 PULL: DIS / IPD GP1 DRIVE PINCTRL189 ...

  • Page 72

    ... PINCTRL162 DVDD_3P3 PULL: IPU / IPU UART0, GPMC, DRIVE GP1 GPMC Address 18 DVDD_3P3 PINCTRL179 PULL: IPU / DIS UART1, GPMC, DRIVE GP1 DVDD_3P3 PINCTRL183 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 73

    ... SD_CLK/ GPMC_A[13 GP1[1] UART1_CTS/ GPMC_A[13 GPMC_A[17]/ GP1[26] GPMC_A[13 GP0[24] Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) (3) OTHER MUXED PULL: IPD / IPD SD, GP1 DRIVE PINCTRL163 DVDD_3P3 PULL: IPU / IPU UART0, GPMC, DRIVE GP1 ...

  • Page 74

    ... GPMC Address 2 PINCTRL223 DVDD_3P3 PULL: IPU / DIS GP0, BOOT DRIVE GPMC Address 1 PINCTRL222 DVDD_3P3 PULL: IPD / DIS GP0 DRIVE GPMC Address 0 PINCTRL221 DVDD_3P3 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 75

    ... AA2 IO GPMC_D[ GPMC_D[3] AA3 IO GPMC_D[2] AB2 IO GPMC_D[1] AA4 IO GPMC_D[0] AC1 IO Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) (3) OTHER MUXED PULL: IPD / IPD - DRIVE PINCTRL249 DVDD_3P3 PULL: IPD / IPD - DRIVE PINCTRL248 DVDD_3P3 PULL: IPD / IPD ...

  • Page 76

    ... HDMI cable at the connector. HDMI Voltage Reference. When HDMI is used, this pin must be connected via an external 5.9K-Ω (±1% tolerance) resistor When the HDMI PHY is powered down, this pin should be left unconnected. Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 77

    ... For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 4.3.1, Pullup and Pulldown Resistors. (3) Specifies the operating IO supply voltage for each signal. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 3-8. I2C Terminal Functions (1) (2) (3) ...

  • Page 78

    ... McASP0 Transmit/Receive Data IOs PULL: IPD / IPD MCB DRIVE PINCTRL135 DVDD_3P3 PULL: IPD / IPD - DRIVE PINCTRL134 DVDD_3P3 PULL: IPD / IPD - DRIVE PINCTRL133 DVDD_3P3 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 79

    ... For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 4.3.1, Pullup and Pulldown Resistors. (3) Specifies the operating IO supply voltage for each signal. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 3-10. McASP1 Terminal Functions (1) (2) (3) ...

  • Page 80

    ... McASP2 Mute Output PINCTRL154 DVDD_3P3 PULL: IPD / IPD MCB DRIVE PINCTRL156 DVDD_3P3 McASP2 Transmit/Receive Data IOs PULL: IPD / IPD - DRIVE PINCTRL155 DVDD_3P3 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 81

    ... For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 4.3.1, Pullup and Pulldown Resistors. (3) Specifies the operating IO supply voltage for each signal. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 3-12. McBSP Terminal Functions (1) (2) (3) ...

  • Page 82

    ... PULL: IPU / IPD - RTC Clock input. Optional 32.768 kHz clock for RTC DRIVE PINCTRL321 reference. If this pin is not used, it should be held low. DVDD_3P3 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 83

    ... I SERDES_CLKN AB33 I ( Input Output High impedance Supply voltage, GND = Ground Analog signal. (2) Specifies the operating IO supply voltage for each signal. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 3-14. PCIe Terminal Functions (1) (2) OTHER PCIE Transmit Data Lane 0. ...

  • Page 84

    ... DRIVE JTAG test port reset input PINCTRL310 DVDD_3P3 PULL: IPU / IPU - DRIVE Emulator pin 4 PINCTRL315 DVDD_3P3 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Section 7.2.13 Table 3-5, GPIO Terminal Table 3-5, GPIO Terminal Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 85

    ... SIGNAL TYPE NAME NO. EMU3 M36 IO EMU2 L37 IO EMU1 L36 IO EMU0 J35 IO Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) (3) OTHER MUXED PULL: IPU / IPU - DRIVE Emulator pin 3 PINCTRL314 DVDD_3P3 PULL: IPU / IPU - DRIVE Emulator pin 2 PINCTRL313 ...

  • Page 86

    ... PULL: IPD / IPD GPMC, GP1 DRIVE Card Detect input PINCTRL164 DVDD_3P3 PULL: IPD / IPD GMC, GP1 DRIVE Card Write Protect input PINCTRL165 DVDD_3P3 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 87

    ... For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 4.3.1, Pullup and Pulldown Resistors. (3) Specifies the operating IO supply voltage for each signal. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: NOTE (1) (2) (3) ...

  • Page 88

    ... DRIVE Serial ATA disk 1 Activity LED output PINCTRL299 DVDD_3P3 PULL: IPD / IPD GP1 DRIVE Serial ATA disk 0 Activity LED output PINCTRL300 DVDD_3P3 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 89

    ... For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 4.3.1, Pullup and Pulldown Resistors. (3) Specifies the operating IO supply voltage for each signal. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 3-19. SPI Terminal Functions (1) (2) (3) ...

  • Page 90

    ... DRIVE Timer4 capture event input or PWM output PINCTRL203 DVDD_3P3 Timer3-1 Watchdog Timer PULL: IPU / IPU - DRIVE Watchdog timer event output PINCTRL319 DVDD_3P3 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 91

    ... For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 4.3.1, Pullup and Pulldown Resistors. (3) Specifies the operating IO supply voltage for each signal. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 3-21. UART0 Terminal Functions (1) (2) (3) ...

  • Page 92

    ... Functions as SD output in IrDA PINCTRL183 DVDD_3P3 mode. PULL: IPU / IPU GPMC, GP1 UART1 Clear to Send Input. Has no function in IrDA DRIVE PINCTRL184 and CIR modes. DVDD_3P3 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 93

    ... For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 4.3.1, Pullup and Pulldown Resistors. (3) Specifies the operating IO supply voltage for each signal. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 3-23. UART2 Terminal Functions (1) (2) (3) ...

  • Page 94

    ... USB1 VBUS input (5 V). The voltage level on this pin is sampled to determine session status When the USB1 PHY is powered down, this pin should be left unconnected. Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 95

    ... For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 4.3.1, Pullup and Pulldown Resistors. (3) Specifies the operating IO supply voltage for each signal. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) (3) OTHER ...

  • Page 96

    ... Video Input 0 Port A Horizontal Sync input. Discrete PULL: IPD / IPD - horizontal synchronization signal for Port A RGB DRIVE PINCTRL32 capture mode or YCbCr capture without embedded DVDD_3P3 syncs ("BT.601" modes). Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 97

    ... VIN[0]A_FLD AL4 I VIN[0]A_D[20]/ AN3 I VIN[0]B_DE VIN[0]A_DE AT3 I Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) (3) OTHER MUXED Video Input 0 Port B Vertical Sync input. Discrete PULL: IPD / IPD VIN[0]A vertical synchronization signal for Port B 8-bit YCbCr ...

  • Page 98

    ... Video Input 1 Port A Data inputs. For 16-bit capture, D[7:0] are Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture, D[7:0] are Port A YCbCr data inputs and D[15:8] are Port B YCbCr data inputs. For VIN[1], only D[15:0] are available. Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 99

    ... VIN[0]A_D[19]/ VIN[1]A_DE/ AK4 VOUT[1]_C[9] VIN[0]A_D[18]/ VIN[1]A_FLD/ AK5 VOUT[1]_C[8] VOUT[0]_G_Y_YC[1]/ VOUT[1]_FLD/ AU8 VIN[1]B_FLD Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) (3) OTHER MUXED PULL: IPD / IPD VOUT[1] I DRIVE PINCTRL19 DVDD_3P3 PULL: IPD / IPD ...

  • Page 100

    ... YUV444 mode they are Y data bits, for Y/C mode they are Y (Luma) data bits and for BT.656 mode they are multiplexed Y/Cb/Cr (Luma and Chroma) data bits. These signals are not used in 8/16/24-bit modes Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 101

    ... VOUT[0]_R_CR[9]/ VOUT[0]_B_CB_C[1]/ AU9 VOUT[1]_Y_YC[9] VOUT[0]_B_CB_C[0]/ VOUT[1]_C[9]/ AR9 VIN[1]B_HSYNC_DE VOUT[0]_R_CR[8]/ VOUT[0]_B_CB_C[0]/ AK10 VOUT[1]_Y_YC[8] Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) (3) OTHER MUXED PULL: IPD / DIS - O DRIVE PINCTRL117 DVDD_3P3 PULL: IPD / DIS ...

  • Page 102

    ... Video Output 0 Field ID output. This is the discrete field identification output. This signal is not used for embedded sync modes. Video Output 0 Active Video output. This is the discrete active video indicator output. This signal is not used for embedded sync modes. Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 103

    ... For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 4.3.1, Pullup and Pulldown Resistors. (3) Specifies the operating IO supply voltage for each signal. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) (3) OTHER ...

  • Page 104

    ... DESCRIPTION Video Output 1 Clock output Video Output 1 Data. These signals represent the 8 bits of Y/YC video data. For Y/C mode they are Y (Luma) data bits and for BT.656 mode they are multiplexed Y/Cb/Cr (Luma and Chroma) data bits. Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 105

    ... VIN[1]A_D[12] VOUT[1]_C[5]/ AP8 VIN[1]A_D[11] VOUT[1]_C[4]/ AN7 VIN[1]A_D[10] VOUT[1]_C[3]/ AM8 VIN[1]A_D[9]/ VOUT[1]_C[2]/ AK6 VIN[1]A_D[8] Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) (3) OTHER MUXED PULL: IPD / DIS VOUT[0] O DRIVE PINCTRL121 DVDD_3P3 PULL: IPD / DIS ...

  • Page 106

    ... Pin supports two functions in silicon revision 2.x devices: 1. Video Output 1 Horizontal Sync output. This is the discrete horizontal synchronization output. This signal is not used for embedded sync modes. 2. Discrete Horizontal Sync for HD-DACs. Functionality is set in SPARE_CTRL0 register as defined in Section 8.10. Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 107

    ... Table 3-30. Video Output 1 [Pins AT9, AR5, AP9, AL5] Terminal Functions (continued) SIGNAL TYPE NAME NO. VOUT[0]_G_Y_YC[0]/ DAC_VOUT[1]_VSYNC/ AP9 VIN[1]B_VSYNC VIN[0]A_D[17]/ VIN[1]A_VSYNC/ AL5 DAC_VOUT[1]_VSYNC Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) (3) OTHER MUXED PULL: IPD / IPD VOUT[0], O DRIVE VIN[1]B DVDD_3P3 PINCTRL29 ...

  • Page 108

    ... Video DAC SD current bias connection. This pin must be connected via an external 1.2-kΩ resistor to VSSA_SD When the SD DACs are powered down, this pin should be left unconnected. Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 109

    ... For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section (3) Specifies the operating IO supply voltage for each signal. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) (3) ...

  • Page 110

    ... Reserved. For proper device operation, this pin must be tied directly Reserved. For proper device operation, this pin must be tied directly Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 111

    ... NO. AM22 RSV59 GND AM21 RSV60 GND AN21 RSV61 GND Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) (2) (3) OTHER Reserved. For proper device operation, this pin must be tied directly Reserved. For proper device operation, this pin must be tied directly to ...

  • Page 112

    ... Note: If the HD DAC is not used, this pin should be connected to a 1.0-V power supply. 1.0-V Analog Power Supply for VDAC SD DAC S - Note: If the SD DAC is not used, this pin should be connected to a 1.0-V power supply. Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 113

    ... DVDD1P8 AJ20, AJ24 VDDA_REF_1P8 AT22 VDDA_HD_1P8 AJ22, AH22 AJ21, AH21, VDDA_SD_1P8 AH20 Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) TYPE OTHER 1.5-V Regulator Power Supply for SATA S - Note: If the SATA is not used, for proper device operation, these pins must be connected to a 1.5-V power supply. ...

  • Page 114

    ... VDD_USB0_3P3 T29, R29 VDD_USB1_3P3 T30, R30 114 Device Pins Product Folder Links: (1) TYPE OTHER S - 3.3-V Power Supply S - 3.3-V Power Supply for USB0 S - 3.3-V Power Supply for USB1 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 115

    ... Y17, Y16, Y15, Y14, Y13, Y8, Y7, Y6, Y5, Y4, W24, W23, W22, W21, W20, W19, W18, W17, W16 ( Input Output High impedance Supply voltage, GND = Ground Analog signal. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 3-34. Ground Terminal Functions (1) TYPE OTHER ...

  • Page 116

    ... Analog GND for PLLs GND - Analog GND for VDAC HD DAC GND - Analog GND for VDAC SD DAC GND - Reference GND for VDAC (1.8 V) GND - Ground for Device Oscillator Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 117

    ... Table 4-3. PLL Control Registers Summary HEX ADDRESS 0x4814 0400 0x4814 0404 0x4814 0408 0x4814 040C 0x4814 0410 Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 4-2 Table 4-1. Control Module Register Map REGISTER GROUP OCP Configuration registers Reserved Device Boot registers ...

  • Page 118

    ... Audio Clock 3 post divider AUDIOPLL_FREQ4 Audio Clock 4 fractional divider AUDIOPLL_DIV4 Audio Clock 4 post divider AUDIOPLL_FREQ5 Audio Clock 5 fractional divider AUDIOPLL_DIV5 Audio Clock 5 post divider - Reserved Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 119

    ... Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: ACRONYM REGISTER NAME DEVICE_ID Device Identification - Reserved INIT_PRESSURE_0 L3 Initiator Pressure ...

  • Page 120

    ... Table 3-1, Boot Terminal Functions), if they are both routed IL Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com level of IL level of all levels for the logic family and V levels. IH Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 121

    ... Additional boot configuration pins determine the following system boot settings as shown in • GPMC CS0 Default Bus Width • GPMC Wait Enable Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: ), and the low-level or high-level input voltages (V I Section 3.2. Submit Documentation Feedback ...

  • Page 122

    ... For more detailed information on booting the device, see the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (literature number SPRUGX8). 122 Device Configurations Product Folder Links: Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 123

    ... The input from each pin is routed to all of the peripherals that share the pin, regardless of the MUXMODE setting. For details, see the table below and the MUXED column in the each of the Terminal Functions tables in Section 3.2. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 4-6. Boot Mode Order BTMODE[ PERIPHERAL BOOTING PREFERRED ...

  • Page 124

    ... VOUT[1]_C[8] VIN[1]A_DE VOUT[1]_C[9] VOUT[1]_C[8] VOUT[1]_CLK VOUT[1]_C[9] VIN[1]B_HSYNC_DE VOUT[1]_HSYNC (silicon revision 1.x) VOUT[1]_AVID DAC_VOUT[1]_HSYNC (silicon revision 2.x) VOUT[1]_VSYNC (silicon revision 1.x) VIN[1]B_VSYNC DAC_VOUT[1]_VSYNC (silicon revision 2.x) VOUT[1]_FLD VIN[1]B_FLD Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 125

    ... PINCTRL74 0 0x4814 0928 PINCTRL75 0 0x4814 092C PINCTRL76 0 0x4814 0930 PINCTRL77 0 0x4814 0934 PINCTRL78 0 0x4814 0938 PINCTRL79 0 Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: PULLDIS 000 0 VOUT[1]_AVID 0 VIN[0]A_HSYNC 0 VIN[0]A_VSYNC 0 VIN[0]A_FLD 0 VIN[0]A_DE 0 VOUT[0]_HSYNC 0 VOUT[0]_VSYNC VOUT[0]_FLD (silicon revision 1 ...

  • Page 126

    ... MCA[0]_AMUTE 0 MCA[0]_AXR[0] 0 MCA[0]_AXR[1] Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com MUXMODE[2:0] 001 010 011 VOUT[1]_Y_YC[2] VOUT[1]_Y_YC[3] VOUT[1]_Y_YC[4] VOUT[1]_Y_YC[5] VOUT[1]_Y_YC[6] VOUT[1]_Y_YC[7] VOUT[1]_Y_YC[8] VOUT[1]_Y_YC[9] Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 127

    ... PINCTRL184 1 0x4814 0AE0 PINCTRL185 0 0x4814 0AE4 PINCTRL186 0 0x4814 0AE8 PINCTRL187 1 0x4814 0AEC PINCTRL188 1 0x4814 0AF0 PINCTRL189 0 Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: PULLDIS 000 0 MCA[0]_AXR[2] MCB_FSX 0 MCA[0]_AXR[3] MCB_FSR 0 MCA[0]_AXR[4] MCB_DX 0 MCA[0]_AXR[5] MCB_DR 0 MCA[1]_ACLKR ...

  • Page 128

    ... GPMC_D[3] 0 GPMC_D[4] 0 GPMC_D[5] 0 GPMC_D[6] 0 GPMC_D[7] 0 GPMC_D[8] 0 GPMC_D[9] 0 GPMC_D[10] Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com MUXMODE[2:0] 001 010 011 GP1[10] GP1[11] GP1[12] GP1[14] GP1[15] GP0[21] GP0[22] GP0[23] GP0[24] GP0[26] GP0[27] GP0[30] GP0[31] Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 129

    ... PINCTRL292 0 0x4814 0C90 PINCTRL293 0 0x4814 0C94 PINCTRL294 0 0x4814 0C98 PINCTRL295 0 0x4814 0C9C PINCTRL296 0 0x4814 0CA0 PINCTRL297 0 0x4814 0CA4 PINCTRL298 0 Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: PULLDIS 000 0 GPMC_D[11] 0 GPMC_D[12] 0 GPMC_D[13] 0 GPMC_D[14] 0 GPMC_D[15] 1 GPMC_CLK GP1[29] 0 EMAC[0]_COL 0 EMAC[0]_CRS ...

  • Page 130

    ... HDMI_HPDET 0 TCLK 1 RTCK 0 TDI 1 TDO 0 TMS 0 TRST 0 EMU0 0 EMU1 0 EMU2 0 EMU3 0 EMU4 0 RESET 0 NMI 0 RSTOUT 0 WD_OUT 1 CLKOUT 0 CLKIN32 0 USB0_DRVVBUS 0 USB1_DRVVBUS Section 3.2. Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com MUXMODE[2:0] 001 010 011 Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 131

    ... Arrows indicate the master-and-slave relationship, not data flow. Master-and-slave connectivity is shown in Table 5-1. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 ...

  • Page 132

    ... HDVICP2-0 C674x Slave (B) HDVICP2-2 HDVICP2-1 Cortex™- A8 DMM Figure 5-1. Interconnect Overview Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Debug McBSP McASP1 GPMC (B) (B) HDVICP2-1 HST (B) PCIe Gen2 (A) SGX530 (B) HDVICP2-0 (B) (B) HDVICP2-2 DDR Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 133

    ... Three HDVICP2 modules are available on the DM8168 and DM8167 devices; two HDVICP2 modules (HDVICP2-0 and HDVICP2-1) are available on the DM8166 and DM8165 devices. (3) SGX530 is available only on the DM8168 and DM8166 device. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SLAVES ...

  • Page 134

    ... SD and SDIO WDT RTC System MMU SmartReflex S martReflex1 DDR _CFG0 DDR _CFG1 Figure 5-2. L4 Architecture Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Spinlock PRCM Control ELM HDMIphy OCPWP McASP 0 McASP 1 McASP 2 Mailbox 0 Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 135

    ... HDMIphy Port0 OCPWP Port0 McASP0 Port0 McASP1 Port0 McASP2 Port0 Mailbox Port0 (1) X, Port0, Port1 = Connection exists. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 5-2. L4 Peripheral Connectivity MASTERS EDMA EDMA EDMA TPTC0 TPTC1 TPTC2 Port1 Port0 Port1 Port1 ...

  • Page 136

    ... DVDD_3P3 for up to 20% of the (6) (7) Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com MIN MAX UNIT -0.3 1.35 V -0.3 1.2 V -0.3 2.45 V -0.3 2. 3.8 V -0.3 2.45 V (3) -0.3 DVDD_DDRx + 0.3 -0.3 2.45 V -0.3 DVDD1P8 + 0.3 (3) -0.3 DVDD_DDRx + 0.3 -0.3 3.8 V -0.3 DVDD_3P3 + 0.3 V signal period 0 95 °C -40 105 -55 150 °C ±1000 V ±250 V Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 137

    ... DDR_VREF is expected to equal 0.5DVDD_DDRx of the transmitting device and to track variations in the DVDD_DDRx. ( the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input signals. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: MIN 0.8 ...

  • Page 138

    ... A thermal model can be provided for thermal simulation to estimate the system thermal environment. Contact your local TI representative for availability. 138 Device Operating Conditions Product Folder Links: MIN (6) 0 -40 20 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com NOM MAX UNIT 95 105 1350 MHz Copyright © 2011–2013, Texas Instruments Incorporated °C ...

  • Page 139

    ... Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. (4) I applies to output-only pins, indicating off-state (Hi-Z) output leakage current. OZ Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) MIN 2.8 360 = MAX 2 ...

  • Page 140

    ... EMIF0 and EMIF1 at 800 MHz, 4480 MBps USB 1x, EMAC 1x, SATA AVS Variable Core voltage = 0.8 V (literature number SPRABK3). Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com TYP MAX UNIT mA (6) 1491 (6) 6463 mA (6) 19 (6) 11 (6) 1241 2.8 pF 2.8 pF Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 141

    ... The active domain has all modules that are only needed when the system is in "active" state. In any of the standby states, these modules are not needed. This domain contains the C674x DSP and HDVPSS peripheral. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 3-33 ...

  • Page 142

    ... ON state. 142 Power, Reset, Clocking, and Interrupts Product Folder Links: NOTE POWER SAVING WAKE-UP LATENCY ~60% Low ~75% Medium ~95% High Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com MEMORY CONTENTS Preserved Preserved Lost Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 143

    ... Recommended capacitors for power supply decoupling are all 0.1 µF in the smallest body size that can be used. Capacitors are more effective in the smallest physical size to limit lead inductance. For example, 0402 sized capacitors are better than 0603 sized capacitors, and so on. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: in ...

  • Page 144

    ... Yes Yes No Yes No Yes No Yes Yes Yes No No Yes Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com (2) (2) (2) LATCHES BOOT ASSERTS PINS RSTOUT PIN Yes Yes Yes Yes No Yes No Yes No Yes No Yes No No Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 145

    ... ICEPick module, the user can perform the following from the Code Composer Studio™ IDE menu: Debug → Advanced Resets → System Reset. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 ...

  • Page 146

    ... The device supports reset isolation for the PCI Express (PCIe) module. This means that the PCI Express subsystem can be reset without resetting the rest of the device. 146 Power, Reset, Clocking, and Interrupts Product Folder Links: Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 147

    ... When that power domain switches from the ON state to the OFF state. 7.2.16 Pin Behaviors at Reset When any reset (other than test reset) described in Hi-Z state except for: Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: 4.3.1. This output is always asserted low when any of the following resets Section 7.2.1 ...

  • Page 148

    ... Product Folder Links: Section 3.2, Terminal Functions. NOTE Table 3-1, Boot Terminal Functions. PARAMETER Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com MIN MAX UNIT (1) 32C ns (1) 12C w(RESET) MIN MAX UNIT (1) 10C Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 149

    ... Device Clocking and Flying Adder PLL section of the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (literature number SPRUGX8). Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Power Supplies Stable Clock Source Stable ...

  • Page 150

    ... To HDVICP2s To L3, HDVPSS To EMAC (A) To SGX530 Audio Clock1 Audio Clock2 Audio Clock3 To RTC HD, SD, TMDS Clocks To DDR PHYs To CEC, UART, and others To L3P, EMIF and DMM DDR Clock4 (Spare) DDR Clock5 (Spare) Figure 7-5. The Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 151

    ... Start-up time (from power up until oscillating at stable frequency of 27 MHz) Crystal Oscillation frequency Parallel Load Capacitance (C1 and C2) Crystal ESR Crystal Shunt Capacitance Crystal Oscillation Mode Crystal Frequency stability Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DEV_MXO DEVOSC_VSS DEVOSC_DVDD18 R d ...

  • Page 152

    ... Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com (1) (2) (3) MIN NOM MAX UNIT 37.037 0.45C 0.55C 0.45C 0.55C 7 150 A ±50 ppm MIN MIN TYP MAX UNIT 100 MHz 50 Ps pk- 700 ps Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 153

    ... Period jitter, CLKIN32 J(CLKIN32) (1) The reference points for the rise and fall transitions are measured CLKIN32 cycle time, in ns. For example, when CLKIN32 frequency is 32768 Hz, use C = 1/32768 s. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: PARAMETER ) IH ) ...

  • Page 154

    ... VCO /N Figure 7-8. Flying-Adder PLL ( ) é ù Ν * Κ ê ú ë FREQ * û Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com 4 4 shows the basic structure of the flying fvco Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 155

    ... PLL Power Supply Filtering The device PLLs are supplied externally via the VDDA_PLL power-supply pins. External filtering must be added on the PLL supply pins to ensure that the requirements in PARAMETER Dynamic noise at VDDA_PLL pins Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: æ ö 6 ...

  • Page 156

    ... MHz 380 MHz DMM, DDR OCP clock 450 MHz 333 MHz 300 MHz SGX530 OCP clock 337.5 MHz 125 MHz GMII clock Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Table 4-3. Table 9-1. Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 157

    ... SYSCLK5 PCIe SYSCLK5 (1) For more information on the available device speed ranges for each part number, see Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: lists the clock source options for each module, along with the Table 7-16. Module Clock Frequencies ...

  • Page 158

    ... DEVICE SPEED MAX. FREQUENCY (MHz) (1) RANGE 125 32.768 250 125 48 Blank 333 2 300 4 337.5 125 125 48 125 125 32.768 125 48 125 Figure 7-9. CLKOUT (1) (2) MIN MAX 10 0.45P 0.55P 0.45P 0.55P 0.05P MIN. OH Copyright © 2011–2013, Texas Instruments Incorporated UNIT ...

  • Page 159

    ... CLKOUT (Divide-by-1) Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links Figure 7-10. CLKOUT Timing Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 TMS320DM8168, TMS320DM8167 TMS320DM8166, TMS320DM8165 SPRS614D – MARCH 2011 – REVISED JANUARY 2013 Power, Reset, Clocking, and Interrupts ...

  • Page 160

    ... Mailbox interrupt 2 iCONT1 sync interrupt iCONT2 sync interrupt Mailbox interrupt 0 Mailbox interrupt 1 Mailbox interrupt 2 iCONT1 sync interrupt iCONT2 sync interrupt Mailbox interrupt 0 Mailbox interrupt 1 Mailbox interrupt 2 iCONT1 sync interrupt iCONT2 sync interrupt SATA Module interrupt Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 161

    ... C0_MISC_INTR_REQ C0_MISC_INTR_PEND C0_RX_THRESH_INTR_REQ C0_RX_THRESH_INTR_PEND C0_RX_INTR_REQ C0_RX_INTR_PEND EMAC SS1 C0_TX_INTR_REQ C0_TX_INTR_PEND C0_MISC_INTR_REQ C0_MISC_INTR_PEND USBSS_INTR_REQ USBSS_INTR_PEND USB0_INTR_REQ USB2.0 SS USB0_INTR_PEND USB1_INTR_REQ USB1_INTR_PEND SLV0P_SWAKEUP Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DESTINATION Cortex™-A8 C674x ...

  • Page 162

    ... Cortex™-A8 C674x Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Legacy interrupt (RC mode only) MSI interrupt (RC mode only) Error interrupt Power Management interrupt Reserved PCIe wakeup Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 163

    ... DDR EMIF4d 0 SYS_ERR_INTR_PEND_N SYS_ERR_INTR DDR EMIF4d 1 SYS_ERR_INTR_PEND_N GPMC GPMC_SINTERRUPT UART 0 NIRQ UART 1 NIRQ UART 2 NIRQ POINTR_REQ Timer1 POINTR_PEND POINTR_REQ Timer2 POINTR_PEND Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DESTINATION Cortex™-A8 C674x ...

  • Page 164

    ... McASP 2 Receive interrupt McBSP Receive Int (legacy mode) McBSP Transmit Int (legacy mode) McBSP Receive Overflow Int (legacy mode) McBSP Common Int Timer interrupt Alarm interrupt GPIO 0 interrupt 1 GPIO 0 interrupt 2 GPIO 1 interrupt 1 GPIO 1 interrupt 2 Reserved Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 165

    ... C674x (EMC) IDMAINT1 EMC_IDMAERR C674x (PBIST) PBISTINT C674x (EFI A) EFIINTA C674x (EFI B) EFIINTB C674x (PMC) PMC_ED UMC_ED1 C674x (UMC) UMC_ED2 C674x (PDC) PDC_INT Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DESTINATION Cortex™-A8 C674x ...

  • Page 166

    ... EMC_CMPA C674x (EMC) EMC_BUSERR 166 Power, Reset, Clocking, and Interrupts Product Folder Links: DESTINATION Cortex™-A8 C674x Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DESCRIPTION Sys C674x Internal Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 167

    ... Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: ACRONYM EMUINT COMMTX COMMRX BENCH ELM_IRQ - NMI - L3DEBUG L3APPINT - EDMACOMPINT EDMAMPERR EDMAERRINT - SATAINT USBSSINT USBINT0 USBINT1 - USBWAKEUP PCIeWAKEUP DSSINT ...

  • Page 168

    ... Timer2 Timer3 I2C0 I2C1 UART0 UART1 UART2 RTC RTC Mailbox McASP0 McASP0 McASP1 McASP1 McASP2 McASP2 McBSP WDTIMER1 Timer4 Timer5 Timer6 Timer7 GPIO 0 GPIO 0 GPIO 1 GPIO 1 GPMC DDR EMIF0 DDR EMIF1 HDVICP2-0 HDVICP2-0 HDVICP2-1 Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 169

    ... C674x module and cannot be changed. Table 7-20. C674x Interrupt Controller Connections INTERRUPT NUMBER 4 (1) Shaded interrupts are reserved for C674x internal use. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: ACRONYM HDVICP1CONT2SYNC HDVICP0MBOXINT HDVICP1MBOXINT HDVICP2MBOXINT HDVICP2CONT1SYNC HDVICP2CONT2SYNC TCERRINT0 TCERRINT1 TCERRINT2 TCERRINT3 ...

  • Page 170

    ... TPCC TPTC0 EMAC0 EMAC0 EMAC0 EMAC0 EMAC1 EMAC1 EMAC1 EMAC1 HDVPSS HDMI WDTIMER1 Timer1 Timer2 Timer3 Timer4 Timer5 Timer6 Timer7 Mailbox I2C0 I2C1 UART0 UART1 UART2 GPIO 0 GPIO 0 GPIO 1 GPIO 1 McASP0 McASP0 McASP1 McASP1 Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 171

    ... Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: ACRONYM MCATXINT2 MCARXINT2 MCBSPINT - HDVICP2CONT1SYNC HDVICP2CONT2SYNC HDVICP2MBOXINT HDVICP0CONT1SYNC HDVICP0CONT2SYNC HDVICP1CONT1SYNC HDVICP1CONT2SYNC HDVICP0MBOXINT HDVICP1MBOXINT INTERR ...

  • Page 172

    ... Data Sheet Timing Reference Point Output Under Test Device Pin (see Note) V ref MAX and V MIN for input clocks MIN (or V MIN) ref MAX (or V MAX) ref IL OL Copyright © 2011–2013, Texas Instruments Incorporated OL ...

  • Page 173

    ... Video DAC guidelines also included to discuss important layout considerations. 8.2 Recommended Clock and Control Signal Transition Behavior All clocks and control signals must transition between V manner. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: and Submit Documentation Feedback ...

  • Page 174

    ... Understanding TI’s PCB Routing Rule-Based DDR2 Timing Specification Application Report (SPRAAV0). 174 Peripheral Information and Timings Product Folder Links: Controller PARAMETER 1 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Table 8-1 -1G UNIT MIN MAX 2 Copyright © 2011–2013, Texas Instruments Incorporated and ...

  • Page 175

    ... DDR[x]_VTP. All other DDR interface pins can be left unconnected. Note that the supported modes for use of the DDR EMIF are 32 bits wide, 16 bits wide, or not used. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: ...

  • Page 176

    ... CS CS CAS CAS RAS RAS WE WE CKE CKE VREF VREF VREF (B) 0.1 µF 0.1 µF 2 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DDR2 (A) Vio 1.8 0.1 µ Ω 1% VREF VREF (B) 0.1 µ Ω 1% Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 177

    ... Vio1.8 is the power supply for the DDR2 memories and the DM816x DDR2 interface. B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin. Figure 8-6. 16-Bit DDR2 High-Level Schematic Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DQ0 DQ7 ...

  • Page 178

    ... Ground Plane Power Signal Internal routing Plane Ground Signal Bottom routing mostly vertical Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com MIN MAX UNIT DDR2-800 x16 x16 Bits 1 2 Devices 84 92 Balls Table 8- Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 179

    ... A 20/10 via may be used if enough power routing resources are available. An 18/10 via allows for more flexible power routing to the processor. (2) For the DDR2 device BGA pad size, see the DDR2 device manufacturer documentation. ( the nominal singled-ended impedance selected for the PCB specified by item 13. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 8-4. ...

  • Page 180

    ... Orientation OFFSET OFFSET Y Table 8-5. Placement Specifications PARAMETER (5) ' offset be as small as possible. Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com MIN MAX UNIT 1660 Mils 1280 Mils 650 Mils 4 w Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 181

    ... These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed (HS) bypass capacitors. Use half of these capacitors for DDR[0] and half for DDR[1]. (2) Only used on 32-bit wide DDR2 memory systems. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Figure ...

  • Page 182

    ... DDR[x]_DQS[3] and DDR[x]_DQS[3] Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com MIN MAX UNIT 0402 10 Mils 250 Mils 2 Vias 1 30 Mils 1 Vias 35 Mils 1 Vias 35 Mils 40 Devices 2.4 μF 8 Devices 0.4 μF lists the signal net classes, and Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 183

    ... VREF is intended to be half the DDR2 power supply voltage and should be created using a resistive divider as shown in 9 shows the layout guidelines for VREF. VREF Bypass Capacitor Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 8-9. Signal Net Class Definitions PROCESSOR PIN NAMES CK ...

  • Page 184

    ... A = A´ + A´´ (2) (3) CACLM-50 (2) (2) Figure 8-10 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com (1) MIN TYP MAX UNIT 2w 25 Mils 25 Mils 4w CACLM CACLM+50 Mils 100 Mils 100 Mils 4w 3w 100 Mils Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 185

    ... PCB that covers both DDR2 and DDR3. 8.3.2.2 DDR3 Device Combinations Since there are several possible combinations of device counts and single- or dual-side mounting, Table 8-14 summarizes the supported device configurations. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: (1) DQLM-50 (2) (3) (4) (1) (5) ...

  • Page 186

    ... MIRRORED ( ( ( Figure 8-13 and Figure 8-14 show the schematic connections for 32-bit Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com (1) DDR3 EMIF WIDTH (BITS Figure 8-13 Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 187

    ... Zo Termination is required. See terminator comments. ZQ Value determined according to the DDR memory device data sheet. Figure 8-13. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: 16-Bit DDR3 Devices DQ15 DQ8 ...

  • Page 188

    ... ODT ODT CS CS BA0 BA0 DDR_VTT BA1 BA1 BA2 BA2 A14 A14 CAS CAS RAS RAS WE WE CKE CKE RST RST DDR_VREF VREFDQ VREFDQ VREFCA VREFCA 0.1 µF Copyright © 2011–2013, Texas Instruments Incorporated DDR_1V5 ...

  • Page 189

    ... Complete stackup specifications are provided in LAYER Table 8-17. Six-Layer PCB Stackup Suggestion LAYER Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: PARAMETER Section 8.3.2.3, Figure Table 8-18. Table 8-16. Minimum PCB Stackup TYPE DESCRIPTION Signal Top routing mostly vertical Plane ...

  • Page 190

    ... The placement does not restrict the side of the PCB DDR3 Controller Y Figure 8-15. Placement Specifications Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com MIN TYP MAX UNIT 0 Z-5 Z Z+5 X2 Copyright © 2011–2013, Texas Instruments Incorporated Mils Mils Mils Mils mm Ω Ω ...

  • Page 191

    ... DDR3 controllers and DDR3 devices. Additional bulk bypass capacitance may be needed for other circuitry. Also note that thus, systems using both controllers have to meet the needs of Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 8-19. Placement Specifications ...

  • Page 192

    ... TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com MIN MAX UNIT 6 Devices μF 140 8-21. MIN TYP MAX UNIT 201 402 10 Mils 400 Mils 70 Devices 5 μF Vias 35 70 Mils 150 Mils 12 Devices 0.85 μF 2 Vias 35 100 Mils 1 Vias 35 60 Mils Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 193

    ... ADDR_CTRL net class Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power sub-plane. VTT should be bypassed near the terminator resistors. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Table 8-22. Clock Net Class Definitions ...

  • Page 194

    ... Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Figure 8-18 shows the topology for the + – Clock Parallel Terminator Rcp A3 AT Cac 0.1 µF Rcp A3 AT Address and Control Terminator Rtt Figure 8-20 Copyright © 2011–2013, Texas Instruments Incorporated DDR_1V5 Vtt ...

  • Page 195

    ... Figure 8-20. ADDR_CTRL Routing for Four Single-Side DDR3 Devices To save PCB space, the four DDR3 memories may be mounted as two mirrored pairs at a cost of increased routing and assembly complexity. ADDR_CTRL, respectively, for four DDR3 devices mirrored in a two-pair configuration. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links ...

  • Page 196

    ... Peripheral Information and Timings Product Folder Links Figure 8-24 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DDR_1V5 Rcp Cac Rcp 0.1 µF Rtt Vtt shows the topology for the Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 197

    ... CK and ADDR_CTRL Routing, Two DDR3 Devices Figure 8-25 shows the CK routing for two DDR3 devices placed on the same side of the PCB. shows the corresponding ADDR_CTRL routing. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DDR Differential CK Input Buffers + – + – ...

  • Page 198

    ... Peripheral Information and Timings Product Folder Links Figure 8-27 and Figure 8-28 show the routing for CK and ADDR_CTRL, Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com DDR_1V5 Rcp Cac Rcp 0.1 µF Rtt Vtt Copyright © 2011–2013, Texas Instruments Incorporated ...

  • Page 199

    ... A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as one bank (CS), 16 bits wide. 8.3.2.14.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device Figure 8-29 shows the topology of the CK net classes and corresponding ADDR_CTRL net classes. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: Rcp ...

  • Page 200

    ... Routed as Differential Pair DDR Address and Control Input Buffers A1 A2 Submit Documentation Feedback TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 www.ti.com Clock Parallel Terminator DDR_1V5 Rcp Cac 0.1 µF Rcp Address and Control Terminator Rtt AT Vtt Figure 8-32 Copyright © 2011–2013, Texas Instruments Incorporated ...