VCBUP8168CCYG2

Manufacturer Part NumberVCBUP8168CCYG2
DescriptionDigital Signal Processors & Controllers - DSP, DSC DaVinci Digital Media Processor
ManufacturerTexas Instruments
SeriesTMS320DM8168
VCBUP8168CCYG2 datasheet
 


Specifications of VCBUP8168CCYG2

RohsyesCoreTMS320DM816x
Data Bus Width32 bitProgram Memory Size32 KB
Data Ram Size256 KBMaximum Clock Frequency1.35 GHz
Number Of Programmable I/os64Number Of Timers7
Device Million Instructions Per Second9000 MIPsOperating Supply Voltage1.5 V, 1.8 V, 3.3 V
Maximum Operating Temperature+ 95 CPackage / CaseFCBGA-1031
Mounting StyleSMD/SMTInstruction Set ArchitectureFloating Point
Interface TypeSPIMinimum Operating Temperature0 C
On-chip AdcNoProcessor SeriesTMS320DM8168
ProductDSPsProgram Memory TypeCache
Supply Current3.3 VSupply Voltage - Min1.5 V
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TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
3.2.20 Digital Video Output Signals
Video output 0 pins AR8 and AL9 and video output 1 pins AT9, AR5, AP9, and AL5 have a
different naming convention and functionality for silicon revision 1.x devices and silicon
revision 2.x devices. These pins are listed separately in
Table 3-27. Video Output 0 Terminal Functions
SIGNAL
TYPE
NAME
NO.
VOUT[0]_CLK
AT14
VOUT[0]_G_Y_YC[9]
AR13
VOUT[0]_G_Y_YC[8]
AU13
VOUT[0]_G_Y_YC[7]
AT13
VOUT[0]_G_Y_YC[6]
AE14
VOUT[0]_G_Y_YC[5]
AM14
VOUT[0]_G_Y_YC[4]
AL14
VOUT[0]_G_Y_YC[3]
AP14
VOUT[0]_G_Y_YC[2]
AE15
VOUT[0]_G_Y_YC[1]/
VOUT[1]_FLD/
AU8
VIN[1]B_FLD
VOUT[0]_G_Y_YC[0]/
VOUT[1]_VSYNC
(silicon revision 1.x)
AP9
DAC_VOUT[1]_VSYNC
(silicon revision 2.x)/
VIN[1]B_VSYNC
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) PULL: A / B, where:
A is the state of the internal pull resistor during POR reset
B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset
IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled
DRIVE: A / B, where;
A is the driving state of the pin during POR reset
B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset
H = Driving High, L = Driving Low, Z = 3-State
For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required,
see
Section
4.3.1, Pullup and Pulldown Resistors.
(3) Specifies the operating IO supply voltage for each signal.
100
Device Pins
Product Folder Links:
NOTE
Table 3-28
(1)
(2) (3)
OTHER
MUXED
PULL: IPD / DIS
-
O
DRIVE: L / H
PINCTRL101
DVDD_3P3
PULL: IPD / DIS
-
O
DRIVE: L / L
PINCTRL109
DVDD_3P3
PULL: IPD / DIS
-
O
DRIVE: L / L
PINCTRL108
DVDD_3P3
PULL: IPD / DIS
-
O
DRIVE: L / L
PINCTRL107
DVDD_3P3
PULL: IPD / DIS
-
O
DRIVE: L / L
PINCTRL106
DVDD_3P3
PULL: IPD / DIS
-
O
DRIVE: L / L
PINCTRL105
DVDD_3P3
PULL: IPD / DIS
-
O
DRIVE: L / L
PINCTRL104
DVDD_3P3
PULL: IPD / DIS
-
O
DRIVE: L / L
PINCTRL103
DVDD_3P3
PULL: IPD / DIS
-
O
DRIVE: L / L
PINCTRL102
DVDD_3P3
PULL: IPD / IPD
VOUT,[1]
O
DRIVE: Z / Z
VIN[1]B
DVDD_3P3
PINCTRL30
PULL: IPD / IPD
VOUT[1],
O
DRIVE: Z / Z
VIN[1]B
DVDD_3P3
PINCTRL29
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www.ti.com
and
Table
3-30.
DESCRIPTION
Video Output 0 Clock output.
Video Output 0 Data. These signals represent the
8 MSBs of G/Y/YC video data. For RGB mode
they are green data bits, for YUV444 mode they
are Y data bits, for Y/C mode they are Y (Luma)
data bits and for BT.656 mode they are
multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
Video Output 0 Data. These signals represent the
2 LSBs of G/Y/YC video data for 10-bit, 20-bit and
30-bit video modes (VOUT0 only). For RGB mode
they are green data bits, for YUV444 mode they
are Y data bits, for Y/C mode they are Y (Luma)
data bits and for BT.656 mode they are
multiplexed Y/Cb/Cr (Luma and Chroma) data
bits. These signals are not used in 8/16/24-bit
modes
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