VCBUP8168CCYG2

Manufacturer Part NumberVCBUP8168CCYG2
DescriptionDigital Signal Processors & Controllers - DSP, DSC DaVinci Digital Media Processor
ManufacturerTexas Instruments
SeriesTMS320DM8168
VCBUP8168CCYG2 datasheet
 


Specifications of VCBUP8168CCYG2

RohsyesCoreTMS320DM816x
Data Bus Width32 bitProgram Memory Size32 KB
Data Ram Size256 KBMaximum Clock Frequency1.35 GHz
Number Of Programmable I/os64Number Of Timers7
Device Million Instructions Per Second9000 MIPsOperating Supply Voltage1.5 V, 1.8 V, 3.3 V
Maximum Operating Temperature+ 95 CPackage / CaseFCBGA-1031
Mounting StyleSMD/SMTInstruction Set ArchitectureFloating Point
Interface TypeSPIMinimum Operating Temperature0 C
On-chip AdcNoProcessor SeriesTMS320DM8168
ProductDSPsProgram Memory TypeCache
Supply Current3.3 VSupply Voltage - Min1.5 V
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4 Device Configurations
4.1
Control Module
The device control module includes status and control logic not addressed within the peripherals or the
remainder of the device infrastructure. This module is the primary point of control for the following areas of
the device:
Functional IO multiplexing
Device status
Static device configuration
Open-core protocol (OCP) interface for standard and customer programmable e-Fuse bit shift
registers.
The control module primarily implements a bank of registers accessible (read and write) by the software
along with some read-only registers carrying status information. Most register bits are exported as control
signals for other logic blocks on the device. Certain control module registers have default values based
upon the device type as decoded from e-Fuse.
The read and write registers can be divided into the following classes:
Static device configuration registers
Status and configuration registers
Boot registers
Table 4-1
shows the general register groupings and
summaries for each group.
ADDRESS OFFSET
0x0000 - 0x0020
0x0024 - 0x003C
0x0040 – 0x00FC
0x0300 - 0x03FC
0x0400 - 0x05FC
0x0600 - 0x07FC
0x0800 - 0x0FFC
Table 4-2. OCP Configuration Registers Summary
HEX ADDRESS
0x4814 0000
0x4814 0004 - 0x4814 000C
0x4814 0010
0x4814 0014 - 0x4814 003C
Table 4-3. PLL Control Registers Summary
HEX ADDRESS
0x4814 0400
0x4814 0404
0x4814 0408
0x4814 040C
0x4814 0410
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links:
Table 4-2
Table 4-1. Control Module Register Map
REGISTER GROUP
OCP Configuration registers
Reserved
Device Boot registers
Reserved
PLL Control registers
Device Configuration registers
PAD Control registers
ACRONYM
REGISTER NAME
CONTROL_REVISION
Control module Revision number
-
Reserved
CONTROL_SYSCONFIG
Idle mode parameters
-
Reserved
ACRONYM
REGISTER NAME
MAINPLL_CTRL
Main PLL base frequency control
MAINPLL_PWD
Main PLL clock output powerdown
MAINPLL_FREQ1
Main Clock 1 fractional divider
MAINPLL_DIV1
Main Clock 1 post divider
MAINPLL_FREQ2
Main Clock 2 fractional divider
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TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165
TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
through
Table 4-4
provide register
SEE
Table 4-2
Table 4-7
Table 4-3
Table 4-4
Section 4.5
Device Configurations
117