VCBUP8168CCYG2

Manufacturer Part NumberVCBUP8168CCYG2
DescriptionDigital Signal Processors & Controllers - DSP, DSC DaVinci Digital Media Processor
ManufacturerTexas Instruments
SeriesTMS320DM8168
VCBUP8168CCYG2 datasheet
 


Specifications of VCBUP8168CCYG2

RohsyesCoreTMS320DM816x
Data Bus Width32 bitProgram Memory Size32 KB
Data Ram Size256 KBMaximum Clock Frequency1.35 GHz
Number Of Programmable I/os64Number Of Timers7
Device Million Instructions Per Second9000 MIPsOperating Supply Voltage1.5 V, 1.8 V, 3.3 V
Maximum Operating Temperature+ 95 CPackage / CaseFCBGA-1031
Mounting StyleSMD/SMTInstruction Set ArchitectureFloating Point
Interface TypeSPIMinimum Operating Temperature0 C
On-chip AdcNoProcessor SeriesTMS320DM8168
ProductDSPsProgram Memory TypeCache
Supply Current3.3 VSupply Voltage - Min1.5 V
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TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
Emulation pins. These pins are only put into a Hi-Z state when POR or global software cold reset is
asserted.
RSTOUT pin.
In addition, the PINCNTL registers, which control pin multiplexing, slew control, enabling the pullup or
pulldown, and enabling the receiver, are reset to the default state. For a description of the RESET_ISO
register, see the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual
(literature number SPRUGX8).
Internal pullup or pulldown (IPU or IPD) resistors are enabled during and immediately after reset as
described in the OTHER column in the tables in
7.2.17 Reset Electrical Data and Timing
If a configuration pin must be routed out from the device, the internal pullup or pulldown (IPU
or IPD) resistor should not be relied upon; TI recommends the use of an external pullup or
pulldown resistor.
Table 7-4. Timing Requirements for Reset
(see
Figure 7-2
and
Figure
7-3)
NO.
1
t
Pulse duration, POR low or RESET low
w(RESET)
2
t
Setup time, boot and configuration pins valid before POR high or RESET
su(CONFIG)
(2)
high
3
t
Hold time, boot and configuration pins valid after POR high or RESET
h(CONFIG)
(2)
high
(1) C = 1/DEV_MXI clock frequency, in ns. The device clock source must be stable and at a valid frequency prior to meeting the t
requirement.
(2) For the list of boot and configuration pins, see
Table 7-5. Switching Characteristics Over Recommended Operating Conditions During Reset
(see
Figure
7-2)
NO.
t
Pulse width, RESET low
w(RSTL)
4
t
Delay time, RESET falling to all IO entering reset state
d(RSTL_IORST)
5
t
Delay time, RESET rising to IO exiting reset state
d(RSTL_IOFUNC)
(1) C = 1/DEV_CLKIN clock frequency, in ns.
148
Power, Reset, Clocking, and Interrupts
Product Folder Links:
Section
3.2, Terminal Functions.
NOTE
Table
3-1, Boot Terminal Functions.
PARAMETER
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TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165
www.ti.com
MIN
MAX
UNIT
(1)
32C
ns
(1)
12C
ns
0
ns
w(RESET)
MIN
MAX
UNIT
(1)
10C
ns
0
14
ns
0
14
ns
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