VCBUP8168CCYG2

Manufacturer Part NumberVCBUP8168CCYG2
DescriptionDigital Signal Processors & Controllers - DSP, DSC DaVinci Digital Media Processor
ManufacturerTexas Instruments
SeriesTMS320DM8168
VCBUP8168CCYG2 datasheet
 


Specifications of VCBUP8168CCYG2

RohsyesCoreTMS320DM816x
Data Bus Width32 bitProgram Memory Size32 KB
Data Ram Size256 KBMaximum Clock Frequency1.35 GHz
Number Of Programmable I/os64Number Of Timers7
Device Million Instructions Per Second9000 MIPsOperating Supply Voltage1.5 V, 1.8 V, 3.3 V
Maximum Operating Temperature+ 95 CPackage / CaseFCBGA-1031
Mounting StyleSMD/SMTInstruction Set ArchitectureFloating Point
Interface TypeSPIMinimum Operating Temperature0 C
On-chip AdcNoProcessor SeriesTMS320DM8168
ProductDSPsProgram Memory TypeCache
Supply Current3.3 VSupply Voltage - Min1.5 V
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TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
Table 7-7. DEV_CLKIN Clock Source Requirements
(see
Figure
7-6)
NO.
1
t
Cycle time, DEV_CLKIN
c(DCK)
2
t
Pulse duration, DEV_CLKIN high
w(DCKH)
3
t
Pulse duration, DEV_CLKIN low
w(DCKL)
4
t
Transition time, DEV_CLKIN
t(DCK)
5
t
Period jitter, DEV_CLKIN (VDACs not used)
J(DCK)
Period jitter, DEV_CLKIN (VDACs used)
S
Frequency stability, DEV_CLKIN
f
(1) The reference points for the rise and fall transitions are measured at V
(2) C = DEV_CLKIN cycle time in ns.
(3)
-S N R
2 0
1 0
B W
Α
=
1 0
*
*
2
*
p
*
B W
2 7
M H z
Where SNR is the desired signal-to-noise ratio and BW is the highest DAC signal bandwidth used in the system (SD = 6 MHz, 720p or
1080i = 30 MHz, 1080p = 60 MHz).
5
1
DEV_CLKIN
7.3.2 SERDES_CLKN and SERDES_CLKP Input Clock
A high-quality, low-jitter differential clock source is required for the PCIe and SATA PHYs. The clock is
required to be AC coupled to the device's SERDES_CLKP and SERDES_CLKN pins according to the
specifications in
Table
7-11. Both the clock source and the coupling capacitors should be placed
physically as close as possible to the processor.
When the PCIe interface is used, the SERDES_CLKN or SERDES_CLKP clock is required to meet the
REFCLK AC specifications outlined in the PCI Express Card Electromechanical Specification (Gen.1 and
Gen.2). When the SATA interface is used, the SERDES_CLKN or SERDES_CLKP clock is required to
meet the specifications in
Table
specifications must be met simultaneously.
Table 7-8. SERDES_CLKN and SERDES_CLKP Clock Source Requirements for SATA
PARAMETER
Clock Frequency
Jitter
Duty Cycle
Rise and Fall Time
An HCSL differential clock source is required to meet the REFCLK AC specifications outlined in the PCI
Express Card Electromechanical Specification, Rev. 2.0, at the input to the AC coupling capacitors. In
addition, LVDS clock sources that are compliant to the above specification, but with the exceptions shown
in
Table
7-9, are also acceptable.
152
Power, Reset, Clocking, and Interrupts
Product Folder Links:
MAX and V
IL
IH
( )
s
1
2
3
Figure 7-6. DEV_CLKIN Timing
7-8. When both the PCIe and SATA interfaces are used, both sets of
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(1) (2) (3)
MIN
NOM
MAX
UNIT
37.037
0.45C
0.55C
0.45C
0.55C
7
150
A
±50
ppm
MIN.
4
4
MIN
TYP
MAX
UNIT
100
MHz
50
Ps pk-pk
40
60
%
700
ps
Copyright © 2011–2013, Texas Instruments Incorporated
ns
ns
ns
ns
ps
s