VCBUP8168CCYG2

Manufacturer Part NumberVCBUP8168CCYG2
DescriptionDigital Signal Processors & Controllers - DSP, DSC DaVinci Digital Media Processor
ManufacturerTexas Instruments
SeriesTMS320DM8168
VCBUP8168CCYG2 datasheet
 


Specifications of VCBUP8168CCYG2

RohsyesCoreTMS320DM816x
Data Bus Width32 bitProgram Memory Size32 KB
Data Ram Size256 KBMaximum Clock Frequency1.35 GHz
Number Of Programmable I/os64Number Of Timers7
Device Million Instructions Per Second9000 MIPsOperating Supply Voltage1.5 V, 1.8 V, 3.3 V
Maximum Operating Temperature+ 95 CPackage / CaseFCBGA-1031
Mounting StyleSMD/SMTInstruction Set ArchitectureFloating Point
Interface TypeSPIMinimum Operating Temperature0 C
On-chip AdcNoProcessor SeriesTMS320DM8168
ProductDSPsProgram Memory TypeCache
Supply Current3.3 VSupply Voltage - Min1.5 V
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TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
5
1
CLKIN32
7.3.4 PLLs
The device contains four embedded PLLs (Main, Audio, Video and DDR) that provide clocks to different
parts of the system. For a high-level view of the device clock architecture, including the PLL reference
clock sources and connections, see
The reference clock for most of the PLLs comes from the DEV_CLKIN input clock. Also, each PLL
supports a bypass mode in which the reference clock can be directly passed to the PLL CLKOUT. All
device PLLs (except the DDR PLL) come-up in bypass mode after reset.
Flying-adder PLLs are used for all the on-chip PLLs.
adder PLL.
fp
fr
/P
The flying-adder PLL has two main components: a multi-phase PLL and the flying-adder synthesizer. The
multi-phase PLL takes an input reference clock (fr), multiplies it with factor, N, and provides a K-phase
output to the flying-adder synthesizer. The flying-adder synthesizer takes this multi-phase clock input and
produces a variable frequency clock (fs). There can be a post divider on this clock which takes in clock fs
and drives out clock fo. The frequency of the clock driven out is given by:
There can be multiple flying-adder synthesizers attached to one multi-phase PLL to generate different
frequencies. In this case, FREQ (4 bits of integer and 24 bits of fractional value) and M (1 to 255) values
can be adjusted for each clock separately, based on the frequency needed. A multi-phase PLL used in
this device has a value of K = 8.
For details on programming the device PLLs, see the PLL chapter of the TMS320DM816x DaVinci Digital
Media Processors Technical Reference Manual (literature number SPRUGX8).
7.3.4.1
PLL Programming Limits
When programming the PLLs, the result of the following equation must be greater than the value shown in
the corresponding PLL table (this determines if the chosen PLL frequency is a valid one).
154
Power, Reset, Clocking, and Interrupts
Product Folder Links:
1
2
3
Figure 7-7. CLKIN32 Timing
Figure
7-4.
Figure 7-8
Flying-Adder
FREQ
Synthesizer
PFD
CP
VCO
/N
Figure 7-8. Flying-Adder PLL
(
)
é
ù
Ν
*
Κ
=
fo
*
fr
ê
ú
(
)
ë
FREQ
*
P
*
M
û
Submit Documentation Feedback
TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165
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4
4
shows the basic structure of the flying-
fs
fo
/M
K
fvco
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