VCBUP8168CCYG2

Manufacturer Part NumberVCBUP8168CCYG2
DescriptionDigital Signal Processors & Controllers - DSP, DSC DaVinci Digital Media Processor
ManufacturerTexas Instruments
SeriesTMS320DM8168
VCBUP8168CCYG2 datasheet
 


Specifications of VCBUP8168CCYG2

RohsyesCoreTMS320DM816x
Data Bus Width32 bitProgram Memory Size32 KB
Data Ram Size256 KBMaximum Clock Frequency1.35 GHz
Number Of Programmable I/os64Number Of Timers7
Device Million Instructions Per Second9000 MIPsOperating Supply Voltage1.5 V, 1.8 V, 3.3 V
Maximum Operating Temperature+ 95 CPackage / CaseFCBGA-1031
Mounting StyleSMD/SMTInstruction Set ArchitectureFloating Point
Interface TypeSPIMinimum Operating Temperature0 C
On-chip AdcNoProcessor SeriesTMS320DM8168
ProductDSPsProgram Memory TypeCache
Supply Current3.3 VSupply Voltage - Min1.5 V
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Table 8-34. EDMA Default Synchronization Events (continued)
EVENT NUMBER
DEFAULT EVENT NAME
59
60
61
62 - 63
8.5.2 EDMA Peripheral Register Descriptions
Table 8-35. EDMA Channel Controller (EDMA TPCC) Control Registers
HEX ADDRESS
0x4900 0000
0x4900 0004
0x4900 0100 - 0x4900 01FC
0x4900 0200
0x4900 0204
0x4900 0208
0x4900 020C
0x4900 0210
0x4900 0214
0x4900 0218
0x4900 021C
0x4900 0240
0x4900 0244
0x4900 0248
0x4900 024C
0x4900 0250
0x4900 0254
0x4900 0258
0x4900 025C
0x4900 0260
0x4900 0284
0x4900 0300
0x4900 0304
0x4900 0308
0x4900 030C
0x4900 0310
0x4900 0314
0x4900 0318
0x4900 031C
0x4900 0320
0x4900 0340
0x4900 0344
0x4900 0348
0x4900 034C
0x4900 0350
0x4900 0354
0x4900 0358
0x4900 035C
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links:
DEFAULT EVENT DESCRIPTION
I2CRXEVT0
I2C0 Receive
I2CTXEVT1
I2C1 Transmit
I2CRXEVT1
I2C1 Receive
-
Unused
ACRONYM
REGISTER NAME
PID
Peripheral Identification
CCCFG
EDMA3CC Configuration
DCHMAP0-63
DMA Channel 0-63 Mappings
QCHMAP0
QDMA Channel 0 Mapping
QCHMAP1
QDMA Channel 1 Mapping
QCHMAP2
QDMA Channel 2 Mapping
QCHMAP3
QDMA Channel 3 Mapping
QCHMAP4
QDMA Channel 4 Mapping
QCHMAP5
QDMA Channel 5 Mapping
QCHMAP6
QDMA Channel 6 Mapping
QCHMAP7
QDMA Channel 7 Mapping
DMAQNUM0
DMA Queue Number 0
DMAQNUM1
DMA Queue Number 1
DMAQNUM2
DMA Queue Number 2
DMAQNUM3
DMA Queue Number 3
DMAQNUM4
DMA Queue Number 4
DMAQNUM5
DMA Queue Number 5
DMAQNUM6
DMA Queue Number 6
DMAQNUM7
DMA Queue Number 7
QDMAQNUM
QDMA Queue Number
QUEPRI
Queue Priority
EMR
Event Missed
EMRH
Event Missed High
EMCR
Event Missed Clear
EMCRH
Event Missed Clear High
QEMR
QDMA Event Missed
QEMCR
QDMA Event Missed Clear
CCERR
EDMA3CC Error
CCERRCLR
EDMA3CC Error Clear
EEVAL
Error Evaluate
DRAE0
DMA Region Access Enable for Region 0
DRAEH0
DMA Region Access Enable High for Region 0
DRAE1
DMA Region Access Enable for Region 1
DRAEH1
DMA Region Access Enable High for Region 1
DRAE2
DMA Region Access Enable for Region 2
DRAEH2
DMA Region Access Enable High for Region 2
DRAE3
DMA Region Access Enable for Region 3
DRAEH3
DMA Region Access Enable High for Region 3
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TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165
TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
Peripheral Information and Timings
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