VCBUP8168CCYG2

Manufacturer Part NumberVCBUP8168CCYG2
DescriptionDigital Signal Processors & Controllers - DSP, DSC DaVinci Digital Media Processor
ManufacturerTexas Instruments
SeriesTMS320DM8168
VCBUP8168CCYG2 datasheet
 


Specifications of VCBUP8168CCYG2

RohsyesCoreTMS320DM816x
Data Bus Width32 bitProgram Memory Size32 KB
Data Ram Size256 KBMaximum Clock Frequency1.35 GHz
Number Of Programmable I/os64Number Of Timers7
Device Million Instructions Per Second9000 MIPsOperating Supply Voltage1.5 V, 1.8 V, 3.3 V
Maximum Operating Temperature+ 95 CPackage / CaseFCBGA-1031
Mounting StyleSMD/SMTInstruction Set ArchitectureFloating Point
Interface TypeSPIMinimum Operating Temperature0 C
On-chip AdcNoProcessor SeriesTMS320DM8168
ProductDSPsProgram Memory TypeCache
Supply Current3.3 VSupply Voltage - Min1.5 V
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TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
8.6
Ethernet Media Access Controller (EMAC)
The device includes two Ethernet Media Access Controller (EMAC) modules which provide an efficient
interface between the device and the networked community. The EMAC supports 10Base-T (10 Mbits per
second [Mbps]) and 100Base-TX (100 Mbps) in either half- or full-duplex mode, and 1000Base-T (1000
Mbps) in full-duplex mode, with hardware flow control and quality-of-service (QOS) support. The EMAC
controls the flow of packet data from the device to an external PHY. A single MDIO interface is pinned out
to control the PHY configuration and status monitoring. Multiple external PHYs can be controlled by the
MDIO interface.
The EMAC module conforms to the IEEE 802.3-2002 standard, describing the Carrier Sense Multiple
Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The IEEE
802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).
Deviating from this standard, the EMAC module does not use the transmit coding error signal, MTXER.
Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC
intentionally generates an incorrect checksum by inverting the frame CRC so that the transmitted frame is
detected as an error by the network. In addition, the EMAC IOs operate at 3.3 V and are not compatible
with 2.5-V IO signaling; therefore, only Ethernet PHYs with 3.3-V IO interface should be used. The EMAC
module incorporates 8K bytes of internal RAM to hold EMAC buffer descriptors and contains the
necessary components to enable the EMAC to make efficient use of device memory and control device
interrupts.
The EMAC module on the device supports two interface modes: Media Independent Interface (MII) and
Gigabit Media Independent Interface (GMII). The MII and GMII interface modes are defined in the IEEE
802.3-2002 standard. The EMAC uses the same pins for the MII and GMII modes of operation. Only one
mode can be used at a time.
The MII and GMII modes-of-operation pins are as follows:
MII:
EMAC[1:0]_TXCLK,
EMAC[1:0]_TXEN,
EMAC[1:0]_RXDV,
MDIO_MCLK, and MDIO_MDIO.
GMII:
EMAC[1:0]_GMTCLK,
EMAC[1:0]_RXD[7:0], EMAC[1:0]_TXEN, EMAC[1:0]_RXDV, EMAC[1:0]_RXER, EMAC[1:0]_COL,
EMAC[1:0]_CRS, MDIO_MCLK, and MDIO_MDIO.
For more detailed information on the EMAC module, see the EMAC and MDIO chapter in the
TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (literature number
SPRUGX8).
8.6.1 EMAC Peripheral Register Descriptions
EMAC0 HEX ADDRESS
EMAC1 HEX ADDRESS
0x4A10 0000
0x4A10 0004
0x4A10 0008
0x4A10 0010
0x4A10 0014
0x4A10 0018
0x4A10 0080
0x4A10 0084
0x4A10 0088
0x4A10 008C
0x4A10 0090
0x4A10 0094
220
Peripheral Information and Timings
Product Folder Links:
EMAC[1:0]_RXCLK,
EMAC[1:0]_TXD[3:0],
EMAC[1:0]_RXER,
EMAC[1:0]_TXCLK,
EMAC[1:0]_RXCLK,
Table 8-37. EMAC Control Registers
ACRONYM
0x4A12 0000
TXIDVER
0x4A12 0004
TXCONTROL
0x4A12 0008
TXTEARDOWN
0x4A12 0010
RXIDVER
0x4A12 0014
RXCONTROL
0x4A12 0018
RXTEARDOWN
0x4A12 0080
TXINTSTATRAW
0x4A12 0084
TXINTSTATMASKED
0x4A12 0088
TXINTMASKSET
0x4A12 008C
TXINTMASKCLEAR
0x4A12 0090
MACINVECTOR
0x4A12 0094
MACEOIVECTOR
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EMAC[1:0]_RXD[3:0],
EMAC[1:0]_COL,
EMAC[1:0]_CRS,
EMAC[1:0]_TXD[7:0],
REGISTER NAME
Transmit Identification and Version
Transmit Control
Transmit Teardown
Receive Identification and Version
Receive Control
Receive Teardown
Transmit Interrupt Status (Unmasked)
Transmit Interrupt Status (Masked)
Transmit Interrupt Mask Set
Transmit Interrupt Clear
MAC Input Vector
MAC End of Interrupt Vector
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