VCBUP8168CCYG2

Manufacturer Part NumberVCBUP8168CCYG2
DescriptionDigital Signal Processors & Controllers - DSP, DSC DaVinci Digital Media Processor
ManufacturerTexas Instruments
SeriesTMS320DM8168
VCBUP8168CCYG2 datasheet
 


Specifications of VCBUP8168CCYG2

RohsyesCoreTMS320DM816x
Data Bus Width32 bitProgram Memory Size32 KB
Data Ram Size256 KBMaximum Clock Frequency1.35 GHz
Number Of Programmable I/os64Number Of Timers7
Device Million Instructions Per Second9000 MIPsOperating Supply Voltage1.5 V, 1.8 V, 3.3 V
Maximum Operating Temperature+ 95 CPackage / CaseFCBGA-1031
Mounting StyleSMD/SMTInstruction Set ArchitectureFloating Point
Interface TypeSPIMinimum Operating Temperature0 C
On-chip AdcNoProcessor SeriesTMS320DM8168
ProductDSPsProgram Memory TypeCache
Supply Current3.3 VSupply Voltage - Min1.5 V
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TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
8.8.2.2
GPMC and NOR Flash Interface Asynchronous Mode Timing
Table 8-56. GPMC and NOR Flash Interface Asynchronous Mode Timing - Internal Parameters
NO.
1
Max. output data generation delay from internal functional clock
2
Max. input data capture delay by internal functional clock
3
Max. chip select generation delay from internal functional clock
4
Max. address generation delay from internal functional clock
5
Max. address valid generation delay from internal functional clock
6
Max. byte enable generation delay from internal functional clock
7
Max. output enable generation delay from internal functional clock
8
Max. write enable generation delay from internal functional clock
9
Max. functional clock skew
Table 8-57. Timing Requirements for GPMC and NOR Flash Interface - Asynchronous Mode
(see
Figure
8-56,
Figure
8-57,
Figure
8-58,
NO.
6
t
Data maximum access time (GPMC_FCLK cycles)
acc(DAT)
Page mode successive data maximum access time (GPMC_FCLK
21
t
acc1-pgmode(DAT)
cycles)
22
t
Page mode first data maximum access time (GPMC_FCLK cycles)
acc2-pgmode(DAT)
(1) H = AccessTime * (TimeParaGranularity + 1)
(2) P = PageBurstAccessTime * (TimeParaGranularity + 1).
Table 8-58. Switching Characteristics Over Recommended Operating Conditions for GPMC and NOR
(see
Figure
8-56,
Figure
8-57,
Figure
8-58,
NO.
1
t
Pulse duration, GPMC_BE0_CLE, GPMC_BE1 valid time
w(nBEV)
2
t
Pulse duration, GPMC_CS[x] low
w(nCSV)
4
t
Delay time, GPMC_CS[x] valid to GPMC_NADV_ALE invalid
d(nCSV-nADVIV)
Delay time, GPMC_CS[x] valid to GPMC_OE_RE invalid (single
5
t
d(nCSV-nOEIV)
read)
10
t
Delay time, address bus valid to GPMC_CS[x] valid
d(AV-nCSV)
Delay time, GPMC_BE0_CLE, GPMC_BE1 valid to GPMC_CS[x]
11
t
d(nBEV-nCSV)
valid
13
t
Delay time, GPMC_CS[x] valid to GPMC_ADV_ALE valid
d(nCSV-nADVV)
14
t
Delay time, GPMC_CS[x] valid to GPMC_OE_RE valid
d(nCSV-nOEV)
(1) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: N = (RdCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: N = (WrCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(2) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For single write: A = (CSWrOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(3) = B - nCS Max Delay + nADV Min Delay
For reading: B = ((ADVRdOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
For writing: B = ((ADVWrOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
(4) = C - nCS Max Delay + nOE Min Delay
C = ((OEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(5) = J - Address Max Delay + nCS Min Delay
J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK
(6) = K - nCS Max Delay + nADV Min Delay
K = ((ADVOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
(7) = L - nCS Max Delay + nOE Min Delay
L = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
242
Peripheral Information and Timings
Product Folder Links:
Figure
8-60)
Flash Interface - Asynchronous Mode
Figure
8-59,
Figure
8-60,
Figure
8-61)
PARAMETER
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TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165
www.ti.com
MIN
MAX
UNIT
6.5
4
6.5
6.5
6.5
6.5
6.5
6.5
100
MIN
MAX
UNIT
(1)
H
cycles
(2)
P
cycles
(1)
H
cycles
MIN
MAX
UNIT
(1)
N
ns
(2)
A
ns
(3)
(3)
B - 0.2
B + 2.0
ns
(4)
(4)
C - 0.2
C + 2.0
ns
(5)
(5)
J - 0.2
J + 2.0
ns
(5)
(5)
J - 0.2
J + 2.0
ns
(6)
(6)
K - 0.2
K + 2.0
ns
(7)
(7)
L - 0.2
L + 2.0
ns
Copyright © 2011–2013, Texas Instruments Incorporated
ns
ns
ns
ns
ns
ns
ns
ns
ps