VCBUP8168CCYG2

Manufacturer Part NumberVCBUP8168CCYG2
DescriptionDigital Signal Processors & Controllers - DSP, DSC DaVinci Digital Media Processor
ManufacturerTexas Instruments
SeriesTMS320DM8168
VCBUP8168CCYG2 datasheet
 


Specifications of VCBUP8168CCYG2

RohsyesCoreTMS320DM816x
Data Bus Width32 bitProgram Memory Size32 KB
Data Ram Size256 KBMaximum Clock Frequency1.35 GHz
Number Of Programmable I/os64Number Of Timers7
Device Million Instructions Per Second9000 MIPsOperating Supply Voltage1.5 V, 1.8 V, 3.3 V
Maximum Operating Temperature+ 95 CPackage / CaseFCBGA-1031
Mounting StyleSMD/SMTInstruction Set ArchitectureFloating Point
Interface TypeSPIMinimum Operating Temperature0 C
On-chip AdcNoProcessor SeriesTMS320DM8168
ProductDSPsProgram Memory TypeCache
Supply Current3.3 VSupply Voltage - Min1.5 V
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Table 8-58. Switching Characteristics Over Recommended Operating Conditions for GPMC and NOR
Flash Interface - Asynchronous Mode (continued)
(see
Figure
8-56,
Figure
8-57,
Figure
8-58,
NO.
15
t
Delay time, GPMC_CS[x] valid to GPMC_DIR high
d(nCSV-DIR)
16
t
Delay time, GPMC_CS[x] valid to GPMC_DIR low
d(nCSV-DIR)
Address invalid duration between 2 successive read or write
17
t
w(AIV)
accesses
Delay time, GPMC_CS[x] valid to GPMC_OE_RE invalid (burst
19
t
d(nCSV-nOEIV)
read)
21
t
Pulse duration, address valid: second, third and fourth accesses
w(AV)
26
t
Delay time, GPMC_CS[x] valid to GPMC_WE valid
d(nCSV-nWEV)
28
t
Delay time, GPMC_CS[x] valid to GPMC_WE invalid
d(nCSV-nWEIV)
29
t
Delay time, GPMC_WE valid to data bus valid
d(nWEV-DV)
30
t
Delay time, data bus valid to GPMC_CS[x] valid
d(DV-nCSV)
Delay time, GPMC_OE_RE valid to GPMC_A[16:1]_D[15:0]
38
t
d(nOEV-AIV)
address phase end
(8) = M - nCS Max Delay + nOE Min Delay
M = ((RdCycleTime - CSOnTime) * (TimeParaGranularity + 1) - 0.5 * CSExtraDelay) * GPMC_FCLK.
Parameter M expression is given as one example of GPMC programming. The IO DIR signal goes from IN to OUT after both
RdCycleTime and BusTurnAround completion. Behavior of the IO direction signal depends on the kind of successive read and write
accesses performed to the memory and multiplexed or non-multiplexed memory addressing scheme, whether the bus keeping feature is
enabled or not. The IO DIR behavior is automatically handled by the GPMC controller.
(9) G = Cycle2CycleDelay * GPMC_FCLK
(10) = I - nCS Max Delay + nOE Min Delay
I = ((OEOffTime + (n - 1) * PageBurstAccessTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) *
GPMC_FCLK
(11) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK
(12) = E - nCS Max Delay + nWE Min Delay
E = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(13) = F - nCS Max Delay + nWE Min Delay
F = ((WEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links:
Figure
8-59,
Figure
8-60,
Figure
8-61)
PARAMETER
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TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165
TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
MIN
MAX
UNIT
(7)
(7)
L - 0.2
L + 2.0
ns
(8)
(8)
M - 0.2
M + 2.0
ns
(9)
G
ns
(10)
(10)
I - 0.2
I + 2.0
ns
(11)
D
ns
(12)
(12)
E - 0.2
E + 2.0
ns
(13)
(13)
F - 0.2
F + 2.0
ns
2.0
ns
(5)
(5)
J - 0.2
J + 2.0
ns
2.0
ns
Peripheral Information and Timings
243