VCBUP8168CCYG2

Manufacturer Part NumberVCBUP8168CCYG2
DescriptionDigital Signal Processors & Controllers - DSP, DSC DaVinci Digital Media Processor
ManufacturerTexas Instruments
SeriesTMS320DM8168
VCBUP8168CCYG2 datasheet
 


Specifications of VCBUP8168CCYG2

RohsyesCoreTMS320DM816x
Data Bus Width32 bitProgram Memory Size32 KB
Data Ram Size256 KBMaximum Clock Frequency1.35 GHz
Number Of Programmable I/os64Number Of Timers7
Device Million Instructions Per Second9000 MIPsOperating Supply Voltage1.5 V, 1.8 V, 3.3 V
Maximum Operating Temperature+ 95 CPackage / CaseFCBGA-1031
Mounting StyleSMD/SMTInstruction Set ArchitectureFloating Point
Interface TypeSPIMinimum Operating Temperature0 C
On-chip AdcNoProcessor SeriesTMS320DM8168
ProductDSPsProgram Memory TypeCache
Supply Current3.3 VSupply Voltage - Min1.5 V
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TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
8.8.2.3
GPMC and NAND Flash Interface Asynchronous Mode Timing
Table 8-59. GPMC and NAND Flash Interface Asynchronous Mode Timing - Internal Parameters
NO.
1
Max. output data generation delay from internal functional clock
2
Max. input data capture delay by internal functional clock
3
Max. chip select generation delay from internal functional clock
4
Max. address latch enable generation delay from internal functional clock
5
Max. command latch enable generation delay from internal functional clock
6
Max. output enable generation delay from internal functional clock
7
Max. write enable generation delay from internal functional clock
8
Max. functional clock skew
Table 8-60. Timing Requirements for GPMC and NAND Flash Interface
(see
Figure
8-64)
NO.
13
t
Data maximum access time (GPMC_FCLK cycles)
acc(DAT)
(1) J = AccessTime * (TimeParaGranularity + 1)
Table 8-61. Switching Characteristics Over Recommended Operating Conditions for GPMC and NAND
(see
Figure
8-62,
Figure
8-63,
Figure
8-64,
NO.
1
t
Pulse duration, GPMC_WE valid time
w(nWEV)
2
t
Delay time, GPMC_CS[x] valid to GPMC_WE valid
d(nCSV-nWEV)
3
t
Delay time, GPMC_BE0_CLE high to GPMC_WE valid
d(CLEH-nWEV)
4
t
Delay time, GPMC_D[15:0] valid to GPMC_WE valid
d(nWEV-DV)
5
t
Delay time, GPMC_WE invalid to GPMC_D[15:0] invalid
d(nWEIV-DIV)
6
t
Delay time, GPMC_WE invalid to GPMC_BE0_CLE invalid
d(nWEIV-CLEIV)
7
t
Delay time, GPMC_WE invalid to GPMC_CS[x] invalid
d(nWEIV-nCSIV)
8
t
Delay time, GPMC_ADV_ALE High to GPMC_WE valid
d(ALEH-nWEV)
9
t
Delay time, GPMC_WE invalid to GPMC_ADV_ALE invalid
d(nWEIV-ALEIV)
10
t
Cycle time, write cycle time
c(nWE)
11
t
Delay time, GPMC_CS[x] valid to GPMC_OE_RE valid
d(nCSV-nOEV)
12
t
Pulse duration, GPMC_OE_RE valid time
w(nOEV)
13
t
Cycle time, read cycle time
c(nOE)
(1) A = (WEOffTime - WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(2) = B + nWE Min Delay - nCS Max Delay
B = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(3) = C + nWE Min Delay - CLE Max Delay
C = ((WEOnTime - ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - ADVExtraDelay)) * GPMC_FCLK
(4) = D + nWE Min Delay - Data Max Delay
D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK
(5) =E + Data Min Delay - nWE Max Delay
E = ((WrCycleTime - WEOffTime) * (TimeParaGranularity + 1) - 0.5 * WEExtraDelay ) * GPMC_FCLK
(6) = F + CLE Min Delay - nWE Max Delay
F = ((ADVWrOffTime - WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - WEExtraDelay )) * GPMC_FCLK
(7) =G + nCS Min Delay - nWE Max Delay
G = ((CSWrOffTime - WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - WEExtraDelay )) * GPMC_FCLK
(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(9) = I + nOE Min Delay - nCS Max Delay
I = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(10) K = (OEOffTime - OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK
(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
250
Peripheral Information and Timings
Product Folder Links:
Flash Interface
Figure
8-65)
PARAMETER
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MIN
MAX
UNIT
6.5
ns
4.0
ns
6.5
ns
6.5
ns
6.5
ns
6.5
ns
6.5
ns
100.0
ps
MIN
MAX
UNIT
(1)
J
cycles
MIN
MAX
UNIT
(1)
A
ns
(2)
(2)
B - 0.2
B + 2.0
ns
(3)
(3)
C - 0.2
C + 2.0
ns
(4)
(4)
D - 0.2
D + 2.0
ns
(5)
(5)
E - 0.2
E + 2.0
ns
(6)
(6)
F - 0.2
F + 2.0
ns
(7)
(7)
G - 0.2
G + 2.0
ns
(3)
(3)
C - 0.2
C + 2.0
ns
(6)
(6)
F - 0.2
F + 2.0
ns
(8)
H
ns
(9)
(9)
I - 0.2
I + 2.0
ns
(10)
K
ns
(11)
L
ns
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