VCBUP8168CCYG2

Manufacturer Part NumberVCBUP8168CCYG2
DescriptionDigital Signal Processors & Controllers - DSP, DSC DaVinci Digital Media Processor
ManufacturerTexas Instruments
SeriesTMS320DM8168
VCBUP8168CCYG2 datasheet
 


Specifications of VCBUP8168CCYG2

RohsyesCoreTMS320DM816x
Data Bus Width32 bitProgram Memory Size32 KB
Data Ram Size256 KBMaximum Clock Frequency1.35 GHz
Number Of Programmable I/os64Number Of Timers7
Device Million Instructions Per Second9000 MIPsOperating Supply Voltage1.5 V, 1.8 V, 3.3 V
Maximum Operating Temperature+ 95 CPackage / CaseFCBGA-1031
Mounting StyleSMD/SMTInstruction Set ArchitectureFloating Point
Interface TypeSPIMinimum Operating Temperature0 C
On-chip AdcNoProcessor SeriesTMS320DM8168
ProductDSPsProgram Memory TypeCache
Supply Current3.3 VSupply Voltage - Min1.5 V
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Table 8-85. AC Coupling Capacitors Requirements
PARAMETER
PCIe AC coupling capacitor value
(1)
PCIe AC coupling capacitor package size
(1) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair, placed side by side.
(2) EIA LxW units; for example, a 0402 is a 40x20 mil (thousandths of an inch) surface-mount capacitor.
8.14.1.2.2 Polarity Inversion
The PCIe specification requires polarity inversion support. This means, for layout purposes, polarity is
unimportant since each signal can change its polarity on-die inside the chip. This means polarity within a
lane is unimportant for layout.
8.14.1.2.3 Lane Reversal
The device supports lane reversal. Since there are two lanes, this means the lanes can be switched in
layout for better PCB routing.
8.14.1.3 Non-Standard PCIe Connections
The following sections contain suggestions for any PCIe connection that is not described in the official
PCIe specification, such as an on-board device-to-device connection, or device-to-other PCIe-compliant
processor connection.
8.14.1.3.1 PCB Stackup Specifications
Table 8-86
shows the stackup and feature sizes required for these types of PCIe connections.
Table 8-86. PCIe PCB Stackup Specifications
PARAMETER
PCB Routing and Plane Layers
Signal Routing Layers
Number of ground plane cuts allowed within PCIe routing region
Number of layers between PCIe routing area and reference plane
PCB Routing clearance
(2)
PCB Trace width
PCB BGA escape via pad size
PCB BGA escape via hole size
(3) (4)
Processor BGA pad size
(1) A reference plane may be a ground plane or the power plane referencing the PCIe signals.
(2) In breakout area.
(3) Non-solder mask defined pad.
(4) Per IPC-7351A BGA pad size guideline.
8.14.1.3.2 Routing Specifications
The PCIe data signal traces must be routed to achieve 100 Ω (±20%) differential impedance and 60 Ω
(±15%) single-ended impedance. The single-ended impedance is required because differential signals are
extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes important.
These requirements are the same as those recommended in the PCIe Motherboard Checklist 1.0
document, available from PCI-SIG.
These impedances are impacted by trace width, trace spacing, distance between signals and referencing
planes, and dielectric material. Verify with a PCB design tool that the trace geometry for both data signal
pairs result in as close to 100 Ω differential impedance and 60 Ω single-ended impedance as possible. For
best accuracy, work with your PCB fabricator to ensure this impedance is met.
Copyright © 2011–2013, Texas Instruments Incorporated
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TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165
TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
MIN
TYP
MAX
UNIT
75
200
nF
0402
0603
EIA
MIN
TYP
MAX
UNIT
4
6
-
Layers
2
3
-
Layers
-
-
0
Cuts
-
-
0
Layers
-
4
-
Mils
-
4
-
Mils
-
20
-
Mils
-
10
Mils
0.3
mm
Peripheral Information and Timings
(2)
285