IDT74SSTU32864ABFG IDT, Integrated Device Technology Inc, IDT74SSTU32864ABFG Datasheet

IDT74SSTU32864ABFG

Manufacturer Part Number

IDT74SSTU32864ABFG

Description

IC BUFFER 1:1/1:2 96-LFBGA

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.IDT74SSTU32864CBFG.pdf (12 pages)

Specifications of IDT74SSTU32864ABFG

Logic Type

1:2 Configurable Registered Buffer

Supply Voltage

1.7 V ~ 1.9 V

Number Of Bits

25, 14

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

96-LFBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

74SSTU32864ABFG

Available stocks

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Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

IDT74SSTU32864ABFG

Manufacturer:

IDT

Quantity:

1 055

Company:

BOSTOCK HK LIMITED

Part Number:

IDT74SSTU32864ABFG

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

IDT74SSTU32864ABFG8

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Current page: 1 of 12
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FEATURES:

• 1:1 and 1:2 registered buffer

• 1.8V Operation

• SSTL_18 style clock and data inputs

• Differential CLK input

• Control inputs compatible with LVCMOS levels

• Flow-through architecture for optimum PCB design

• Latch-up performance exceeds 100mA

• ESD >2000V per MIL-STD-883, Method 3015; >200V using

• Maximum operating frequency: 340MHz

• Available in 96-pin LFBGA package

COMMERCIAL TEMPERATURE RANGE

APPLICATIONS:

• Ideally suited for DDR2-400/533 (PC2 - 3200/ 4200) registered

• Along with CSPU877/A/D, zero delay PLL clock buffer, provides

• SSTU32864 is optimized for DDR2 Raw cards B and C

• SSTU32864A is optimized for DDR2 Raw card A

• SSTU32864C/D/G are optimized for DDR2 Raw cards A, B, and C

• SSTU32864G has control pins for output slew rate control

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

IDT74SSTU32864/A/C/D/G

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

machine model (C = 200pF, R = 0)

DIMM applications

complete solution for DDR2-400/533 DIMMs

2006 Integrated Device Technology, Inc.

1:1 AND 1:2 REGISTERED

BUFFER WITH 1.8V SSTL I/O

DESCRIPTION:

designed for 1.7V to 1.9V V

compatible with the JEDEC standard for SSTL_18. The control inputs are

LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized

to drive the DDR2 DIMM load.

are registered at the crossing of CLK going high and CLK going low.

A configuration (when low) to B configuration (when high). The C1 input

controls the configuration from the 25-bit 1:1 (when low) to 14-bit 1:2 (when

high).

(RESET) is low, the differential input receivers are disabled, and undriven

(floating) data, clock, and reference voltage (V

addition, when RESET is low all registers are reset, and all outputs are

forced low. The LVCMOS RESET and Cx inputs must always be held at

a valid logic high or low level.

been supplied, RESET must be held in the low state during power up.

asynchronous with respect to CLK and CLK. Therefore, no timing

relationship can be guaranteed between the two. When entering reset, the

to the time to disable the differential input receivers. However, when coming

out of a reset, the register will become active quickly, relative to the time to

enable the differential input receivers. As long as the data inputs are low,

and the clock is stable during the time from the low-to-high transition of

RESET until the input receivers are fully enabled, the design of the

SSTU32864 must ensure that the outputs will remain low, thus ensuring no

glitches on the outputs.

from changing states when both DCS and CSR inputs are high. If either

DCS or CSR input is low, the device will function normally. The RESET

input has priority over the DCS control and will force the inputs low. If the

DCS control functionality is not desired, then the CSR input can be hard-

wired to ground, in which case the set-up time requirement for DCS would

be the same as for the other D data inputs.

optimize the signal integrity on the DIMM.

The SSTU32864 is a 25-bit 1:1 / 14-bit 1:2 configurable registered buffer

The SSTU32864 operates from a differential clock (CLK and CLK). Data

The C0 input controls the pinout configuration of the 1:2 pinout from the

This device supports low-power standby operation. When the reset input

To ensure defined outputs from the register before a stable clock has

In the DDR2 DIMM application, RESET is specified to be completely

The device monitors both DCS and CSR inputs and will gate the outputs

The SSTU32864G has two slew control pins (Z

COMMERCIAL TEMPERATURE RANGE

operation. All clock and data inputs are

IDT74SSTU32864/

REF

) inputs are allowed. In

APRIL 2006

and Z

A/C/D/G

DSC-5980/27

) used to

Related parts for IDT74SSTU32864ABFG

IDT74SSTU32864ABFG Summary of contents

Page 1

IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through ...

Page 2

IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O FUNCTIONAL BLOCK DIAGRAM (1:2) RESET CLK CLK V REF DCKE DODT DCS CSR OTHER CHANNELS COMMERCIAL TEMPERATURE RANGE QCKE QCKE QODT ...

Page 3

IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O PIN CONFIGURATION (TYPE A) 6 Q2B Q3B QCKEB QODTB 5 QCKEA Q2A Q3A QODTA 4 V GND V GND GND V GND DD REF 2 NC ...

Page 4

IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O FUNCTIONAL BLOCK DIAGRAM (1:1) RESET CLK1 CLK1 V REF DCKE DODT DCS CSR OTHER CHANNELS COMMERCIAL TEMPERATURE RANGE 1D C1 QCKE QOTD R 1D ...

Page 5

IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O PIN CONFIGURATION NC Q15 Q16 QCKE Q3 QODT 4 V GND V GND GND V GND DD REF 2 NC D15 D16 ...

Page 6

IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O FUNCTION TABLE (EACH FLIP-FLOP) (1) RESET DCS CSR ...

Page 7

IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O ABSOLUTE MAXIMUM RATINGS Symbol Description V Supply Voltage Range DD (2,3) V Input Voltage Range I (2,3) V Output Voltage Range O I Input Clamp Current V < ...

Page 8

IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O OPERATING CHARACTERISTICS, T Symbol Parameter V Supply Voltage DD V Reference Voltage REF V Termination Voltage TT V Input Voltage High-Level Input Voltage Low-Level ...

Page 9

IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE Symbol Parameter f (1) Clock Frequency CLOCK tw Pulse Duration, CLK, CLK HIGH or LOW ACT (2) t Differential Inputs Active Time ...

Page 10

IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O TEST CIRCUITS AND WAVEFORMS (V CLK Inputs LVCMOS RESET Input t INACT I DD 10% Voltage and Current Waveforms Inputs Active and Inactive Times t W Input ...

Page 11

IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O TEST CIRCUITS AND WAVEFORMS (V Output Output NOTES includes probe and jig capacitance All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ...

Page 12

IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O ORDERING INFORMATION XX XXX IDT SSTU32 Temp. Range Device Type XX X Package Shipping Carrier 8 Blank BF BFG 864 864A 864C 864D 864G 74 CORPORATE HEADQUARTERS for SALES: 6024 ...

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