PI74SSTVF16859AE Pericom Semiconductor, PI74SSTVF16859AE Datasheet
PI74SSTVF16859AE
Manufacturer Part Number
PI74SSTVF16859AE
Description
IC REG BUFFER 13-26BIT 64-TSSOP
Manufacturer
Pericom Semiconductor
Series
74SSTVFr
Datasheet
1.PI74SSTVF16859AE.pdf
(8 pages)
Specifications of PI74SSTVF16859AE
Logic Type
13-Bit to 26-Bit Registered Buffer, DDR
Supply Voltage
2.3 V ~ 2.7 V
Number Of Bits
13, 26
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TSSOP
Logic Family
SSTV
Logical Function
Registered Buffer
Number Of Elements
1
Number Of Inputs
13
Number Of Outputs
26
High Level Output Current
-16mA
Low Level Output Current
16mA
Propagation Delay Time
5ns
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
210(Min)MHz
Mounting
Surface Mount
Pin Count
64
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Dc
0517
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Product Features
• PI74 SSTVF16859 is designed for low-voltage operation,
• Supports SSTL_2 Class I specifications on outputs
• All Inputs are SSTL_2 Compatible, except RESET
• Designed for DDR Memory
• Flow-Through Architecture
• Packages:
Logic Block Diagram - TSSOP
Logic Block Diagram - QFN
Product Pin Description
C
C
Q
G
R
D
V
V
V
2.5V for PC1600 ~ PC2700; 2.6V for PC3200
which is LVCMOS.
56-pin, Plastic Very Thin Fine Pitch Quad Flat
(Lead-free packages are available)
RESET
RESET
P
E
L
L
N
D
D
R
V
V
No Lead QFN (ZB)
CLK
CLK
CLK
CLK
n i
S
K
K
E
REF
REF
D
D
D
D1
D1
F
E
Q
N
08-0291
T
a
m
48
49
51
35
45
35
36
38
24
32
e
TO 12 OTHER CHANNELS
TO 12 OTHER CHANNELS
C
C
r G
C
O
R
D
D
I
p n
s e
o l
o l
o
a
a
u
u o
a t
a t
e r
p t
t u
k c
k c
t e
d n
t u
I
O
S
R
A (
p n
I
I
u
p n
p n
u
S
e
p p
p t
r e f
, t u
i t c
u
, t u
, t u
p p
, t u
y l
e v
n e
D
y l
P
N
V
e c
- 1
Q
L
D
s o
o
g e
V
o
- 1
D
a t l
e
o
V
i t i
) w
R
D
R
D
i t a
c s
3 1
a t l
Q
o
e g
e v
CLK
CLK
a t l
e v
3 1
i r
e g
L
D
e g
t p
V
D
f i
C
o i
r e f
f i
M
r e f
n
n e
O
n e
a i t
S
a i t
I l
I l
16
p n
32
7
22
p n
t u
t u
Q1A
Q1A
Q1B
Q1B
1
Product Description
Pericom Semiconductor’s PI74SSTVF16859 logic circuit is produced
using the Company’s advanced sub-micron CMOS technology,
achieving industry leading speed.
All inputs are compatible with the JEDEC standard for SSTL_2,
except the LVCMOS reset (RESET) input. All outputs are SSTL_2,
Class II compatible.
The device operates from a differential clock (CLK and CLK). Data
registered at the crossing of CLK going HIGH, and CLK going LOW.
The PI74SSTVF16859 supports low-power standby operation. When
RESET is LOW, the differential input receivers are disabled, and
undriven (floating) data, clock and reference voltage (V
are allowed. In addition, when RESET is LOW, all registers are reset,
and all outputs are forced LOW. The LVCMOS RESET input must
always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock
has been supplied, RESET must be held in the LOW state during
power up.
In the DDR DIMM application, RESET is specified to be completely
asynchronous with respect to CLK and CLK. Therefore, no timing
relationship can be guaranteed between the two. When entering
RESET, the register will be cleared and the outputs will be driven
LOW quickly, relative to the time to disable the differential input
receivers, thus ensuring no glitches on the output. However, when
coming out of RESET, the register will become active quickly, relative
to the time to enable the differential input receivers. When the data
inputs are LOW, and the clock is stable, during the time from the
LOW-to-HIGH transition of RESET until the input receivers
are fully enabled, the design must ensure that the outputs will
remain LOW.
Pericom’s PI74SSTVF16859 is characterized for operation from
0°C to 70°C.
Truth
Notes:
1. H = High Signal Level
R
L = Low Signal Level
↑ = Transition LOW-to-HIGH
↓ = Transition HIGH-to-LOW
X = Irrelevant or floating
E
H
Η
H
L
S
E
T
Tabl e
13-Bit to 26-Bit Registered Buffer
(1)
F
L
C
o l
X
r o
L
i t a
↑
↑
r o
K
H
g n
n I
p
u
s t
F
L
C
X
o l
r o
L
i t a
↓
↓
r o
K
g n
H
PI74SSTVF16859
2. Output level before the
indicated steady state
input conditions were
established.
F
o l
X
D
H
X
L
i t a
r o
g n
PS8657C
O
REF
Q
u
p t
Q
H
L
L
o
) inputs
(
u
) 2
10/07/08
s t
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PI74SSTVF16859AE Summary of contents
Page 1
... E F 08-0291 Product Description Pericom Semiconductor’s PI74SSTVF16859 logic circuit is produced using the Company’s advanced sub-micron CMOS technology, achieving industry leading speed. All inputs are compatible with the JEDEC standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible ...
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... Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 08-0291 DESCRIPTION: 56-contact, Thin Fine Pitch Quad Flat No-lead (TQFN) PACKAGE CODE: ZB56 DOCUMENT CONTROL #: PD-2008 Pericom Semiconductor Corporation 8 PI74SSTVF16859 13-Bit to 26-Bit Registered Buffer DATE: 02/17/06 REVISION ° ° ...