LCMXO640C-4MN100I Lattice, LCMXO640C-4MN100I Datasheet - Page 13

• Manufacturer Part Number: LCMXO640C-4MN100I
• Description: CPLD - Complex Programmable Logic Devices 640 LUTs 74 IO 1.8/2 .5/3.3V -4 Spd I
• Manufacturer: Lattice

Specifications of LCMXO640C-4MN100I

• Rohs: yes
• Memory Type: SRAM
• Number Of Macrocells: 320
• Maximum Operating Frequency: 550 MHz
• Delay Time: 4.2 ns
• Number Of Programmable I/os: 74
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Package / Case: CSBGA-100
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 1800
• Supply Current: 17 mA
• Supply Voltage - Max: 3.465 V
• Supply Voltage - Min: 1.71 V

Lattice Semiconductor
Table 2-5. PLL Signal Descriptions
For more information on the PLL, please see details of additional technical documentation at the end of this data
sheet.
sysMEM Memory
The MachXO1200 and MachXO2280 devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists
of a 9-Kbit RAM, with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be
used in a variety of depths and widths as shown in Table 2-6.
Table 2-6. sysMEM Block Configurations
CLKI
CLKFB
RST
CLKOS
CLKOP
CLKOK
LOCK
CLKINTFB
DDAMODE
DDAIZR
DDAILAG
DDAIDEL[2:0]
Signal
I/O
O
O
O
O
O
I
I
I
I
I
I
I
Clock input from external pin or routing
PLL feedback input from PLL output, clock net, routing/external pin or internal feedback from
CLKINTFB port
“1” to reset the input clock divider
PLL output clock to clock tree (phase shifted/duty cycle changed)
PLL output clock to clock tree (No phase shift)
PLL output to clock tree through secondary clock divider
“1” indicates PLL LOCK to CLKI
Internal feedback source, CLKOP divider output before CLOCKTREE
Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static)
Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on
Dynamic Delay Lag/Lead. “1”: Lag, “0”: Lead
Dynamic Delay Input
Single Port
True Dual Port
Pseudo Dual Port
FIFO
Memory Mode
2-10
Configurations
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
256 x 36
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
512 x 18
Description
MachXO Family Data Sheet
Architecture