LCMXO1200E-4TN144I Lattice, LCMXO1200E-4TN144I Datasheet - Page 46

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LCMXO1200E-4TN144I

Manufacturer Part Number
LCMXO1200E-4TN144I
Description
CPLD - Complex Programmable Logic Devices 1200 LUTs 113 IO 1.2 V -4 Spd I
Manufacturer
Lattice
Datasheet

Specifications of LCMXO1200E-4TN144I

Rohs
yes
Memory Type
SRAM
Number Of Macrocells
600
Maximum Operating Frequency
550 MHz
Delay Time
4.4 ns
Number Of Programmable I/os
113
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Package / Case
TQFP-144
Mounting Style
SMD/SMT
Factory Pack Quantity
300
Supply Current
18 mA
Supply Voltage - Max
1.26 V
Supply Voltage - Min
1.14 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LCMXO1200E-4TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
www.latticesemi.com
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
June 2009
Signal Descriptions
General Purpose
P[Edge] [Row/Column 
Number]_[A/B/C/D/E/F]
GSRN
TSALL
NC
GND
V
V
V
SLEEPN
PLL and Clock Functions (Used as user programmable I/O pins when not used for PLL or clock pins)
[LOC][0]_PLL[T, C]_IN
[LOC][0]_PLL[T, C]_FB
PCLK [n]_[1:0]
Test and Programming (Dedicated pins)
TMS
TCK
TDI
TDO
1. Applies to MachXO “C” devices only. NC for “E” devices.
CC
CCAUX
CCIOx
Signal Name
1
I/O
I/O
O
I
I
I
I
I
I
[Edge] indicates the edge of the device on which the pad is located. Valid edge designa-
tions are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on which the
PIO Group exists. When Edge is T (Top) or (Bottom), only need to specify Row Number.
When Edge is L (Left) or R (Right), only need to specify Column Number.
[A/B/C/D/E/F] indicates the PIO within the group to which the pad is connected.
Some of these user programmable pins are shared with special function pins. When not
used as special function pins, these pins can be programmed as I/Os for user logic.
During configuration of the user-programmable I/Os, the user has an option to tri-state the
I/Os and enable an internal pull-up resistor. This option also applies to unused pins (or
those not bonded to a package pin). The default during configuration is for user-program-
mable I/Os to be tri-stated with an internal pull-up resistor enabled. When the device is
erased, I/Os will be tri-stated with an internal pull-up resistor enabled.
Global RESET signal (active low). Dedicated pad, when not in use it can be used as an I/O
pin.
TSALL is a dedicated pad for the global output enable signal. When TSALL is high all the
outputs are tristated. It is a dual function pin. When not in use, it can be used as an I/O pin.
No connect.
GND - Ground. Dedicated pins.
VCC - The power supply pins for core logic. Dedicated pins.
VCCAUX - the Auxiliary power supply pin. This pin powers up a variety of internal circuits
including all the differential and referenced input buffers. Dedicated pins.
V
Sleep Mode pin - Active low sleep pin.þ When this pin is held high, the device operates
normally.þ This pin has a weak internal pull-up, but when unused, an external pull-up to
V
fied time.
Reference clock (PLL) input Pads: [LOC] indicates location. Valid designations are ULM
(Upper PLL) and LLM (Lower PLL). T = true and C = complement.
Optional feedback (PLL) input Pads: [LOC] indicates location. Valid designations are ULM
(Upper PLL) and LLM (Lower PLL). T = true and C = complement.
Primary Clock Pads, n per side.
Test Mode Select input pin, used to control the 1149.1 state machine.
Test Clock input pin, used to clock the 1149.1 state machine.
Test Data input pin, used to load data into the device using an 1149.1 state machine.
Output pin -Test Data output pin used to shift data out of the device using 1149.1.
CCIO
CC
is recommended. When driven low, the device moves into Sleep mode after a speci-
- The power supply pins for I/O Bank x. Dedicated pins.
4-1
MachXO Family Data Sheet
Descriptions
Pinout Information
DS1002
Data Sheet DS1002
Pinouts_01.8

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