LCMXO256E-5MN100C Lattice, LCMXO256E-5MN100C Datasheet - Page 25

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LCMXO256E-5MN100C

Manufacturer Part Number
LCMXO256E-5MN100C
Description
CPLD - Complex Programmable Logic Devices 256 LUTs 78 IO 1.2V -5 Spd
Manufacturer
Lattice
Datasheet

Specifications of LCMXO256E-5MN100C

Rohs
yes
Memory Type
SRAM
Number Of Macrocells
128
Maximum Operating Frequency
600 MHz
Delay Time
3.5 ns
Number Of Programmable I/os
78
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
CSBGA-100
Mounting Style
SMD/SMT
Factory Pack Quantity
1800
Supply Current
10 mA
Supply Voltage - Max
1.26 V
Supply Voltage - Min
1.14 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LCMXO256E-5MN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Device Configuration
All MachXO devices contain a test access port that can be used for device configuration and programming.
The non-volatile memory in the MachXO can be configured in two different modes:
The SRAM configuration memory can be configured in three different ways:
Figure 2-22 provides a pictorial representation of the different programming modes available in the MachXO
devices. On power-up, the SRAM is ready to be configured with IEEE 1149.1 serial TAP port using IEEE 1532 pro-
tocols.
Leave Alone I/O
When using IEEE 1532 mode for non-volatile memory programming, SRAM configuration, or issuing a refresh
command, users may specify I/Os as high, low, tristated or held at current value. This provides excellent flexibility
for implementing systems where reconfiguration or reprogramming occurs on-the-fly.
TransFR (Transparent Field Reconfiguration)
TransFR (TFR) is a unique Lattice technology that allows users to update their logic in the field without interrupting
system operation using a single ispVM command. See TN1087,
tion Using TransFR Technology
Security
The MachXO devices contain security bits that, when set, prevent the readback of the SRAM configuration and
non-volatile memory spaces. Once set, the only way to clear the security bits is to erase the memory space.
For more information on device configuration, please see details of additional technical documentation at the end
of this data sheet.
• In IEEE 1532 mode via the IEEE 1149.1 port. In this mode, the device is off-line and I/Os are controlled by
• In background mode via the IEEE 1149.1 port. This allows the device to remain operational in user mode
• At power-up via the on-chip non-volatile memory.
• After a refresh command is issued via the IEEE 1149.1 port.
• In IEEE 1532 mode via the IEEE 1149.1 port.
BSCAN registers.
while reprogramming takes place.
for details.
2-22
Minimizing System Interruption During Configura-
MachXO Family Data Sheet
Architecture

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