LCMXO640E-5TN144C

Manufacturer Part NumberLCMXO640E-5TN144C
DescriptionCPLD - Complex Programmable Logic Devices 640 LUTs 113 IO 1.2V -5 Spd
ManufacturerLattice
LCMXO640E-5TN144C datasheet
 

Specifications of LCMXO640E-5TN144C

RohsyesMemory TypeSRAM
Number Of Macrocells320Maximum Operating Frequency600 MHz
Delay Time3.5 nsNumber Of Programmable I/os113
Operating Supply Voltage1.2 VMaximum Operating Temperature+ 85 C
Minimum Operating Temperature0 CPackage / CaseTQFP-144
Mounting StyleSMD/SMTFactory Pack Quantity300
Supply Current14 mASupply Voltage - Max1.26 V
Supply Voltage - Min1.14 V  
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MachXO Family Data Sheet
DS1002 Version 02.9, July 2010

LCMXO640E-5TN144C Summary of contents

  • Page 1

    MachXO Family Data Sheet DS1002 Version 02.9, July 2010 ...

  • Page 2

    ... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

  • Page 3

    ... The ispLEVER design tools from Lattice allow complex designs to be efficiently implemented using the MachXO family of devices. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the MachXO device ...

  • Page 4

    ... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

  • Page 5

    ... Lattice Semiconductor Figure 2-1. Top View of the MachXO1200 Device sysMEM Embedded Block RAM (EBR) sysCLOCK PLL JTAG Port 1. Top view of the MachXO2280 device is similar but with higher LUT count, two PLLs, and three EBR blocks. Figure 2-2. Top View of the MachXO640 Device Programmable ...

  • Page 6

    ... Lattice Semiconductor Figure 2-3. Top View of the MachXO256 Device JTAG Port Programmable Function Units with RAM (PFUs) PFU Blocks The core of the MachXO devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM, and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic, and Distributed ROM functions ...

  • Page 7

    ... Lattice Semiconductor There are 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent Slice/PFU). There are 7 outputs the routing and one to the carry-chain (to the adjacent Slice/PFU). Table 2-1 lists the sig- nals associated with each Slice. Figure 2-5. Slice Diagram ...

  • Page 8

    ... Lattice Semiconductor Modes of Operation Each Slice is capable of four modes of operation: Logic, Ripple, RAM, and ROM. The Slice in the PFF is capable of all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks. Table 2-2. Slice Modes PFU Slice LUT 4x2 or LUT 5x1 ...

  • Page 9

    ... Lattice Semiconductor Figure 2-6. Distributed Memory Primitives SPR16x2 AD0 AD1 AD2 AD3 DI0 DI1 WRE CK ROM16x1 AD0 AD1 AD2 AD3 ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is accomplished through the programming interface during configuration. ...

  • Page 10

    ... Lattice Semiconductor The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. Clock/Control Distribution Network The MachXO family of devices provides global signals that are available to all PFUs. These signals consist of four primary clocks and four secondary clocks ...

  • Page 11

    ... Lattice Semiconductor Figure 2-8. Primary Clocks for MachXO1200 and MachXO2280 Devices Routing Four secondary clocks are generated from four 16:1 muxes as shown in Figure 2-9. Four of the secondary clock sources come from dual function clock pins and 12 come from internal routing. Figure 2-9. Secondary Clocks for MachXO Devices ...

  • Page 12

    ... Lattice Semiconductor sysCLOCK Phase Locked Loops (PLLs) The MachXO1200 and MachXO2280 provide PLL support. The source of the PLL input divider can come from an external pin or from internal routing. There are four sources of feedback signals to the feedback divider: from CLKINTFB (internal feedback port), from the global clock nets, from the output of the post scalar divider, and from the routing (or from an external pin) ...

  • Page 13

    ... Lattice Semiconductor Table 2-5. PLL Signal Descriptions Signal I/O CLKI I Clock input from external pin or routing I PLL feedback input from PLL output, clock net, routing/external pin or internal feedback from CLKFB CLKINTFB port RST I “1” to reset the input clock divider CLKOS O PLL output clock to clock tree (phase shifted/duty cycle changed) ...

  • Page 14

    ... ROM. Memory Cascading Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual, Pseudo-Dual Port and FIFO Modes Figure 2-12 shows the five basic memory configurations and their input/output names ...

  • Page 15

    ... Lattice Semiconductor The EBR memory supports three forms of write behavior for single or dual port operation: 1. Normal – data on the output appears only during the read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths. ...

  • Page 16

    ... Lattice Semiconductor Figure 2-13. Memory Core Reset RSTA RSTB GSRN For further information on the sysMEM EBR block, see the details of additional technical documentation at the end of this data sheet. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-14 ...

  • Page 17

    ... Lattice Semiconductor PIO Groups On the MachXO devices, PIO cells are assembled into two different types of PIO groups, those with four PIO cells and those with six PIO cells. PIO groups with four IOs are placed on the left and right sides of the device while PIO groups with six IOs are placed on the top and bottom ...

  • Page 18

    ... Lattice Semiconductor output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 2-17 shows the MachXO PIO logic. The tristate control signal is multiplexed from the output data signals and their complements. In addition a global signal (TSALL) from a dedicated pad can be used to tristate the sysIO buffer. ...

  • Page 19

    ... Lattice Semiconductor of the devices also support differential input buffers. PCI clamps are available on the top Bank I/O buffers. The PCI clamp is enabled after V CC figured.  The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer ...

  • Page 20

    ... Lattice Semiconductor Table 2-8. I/O Support Device by Device MachXO256 Number of I/O Banks 2 Single-ended  (all I/O Banks) Type of Input Buffers Single-ended buffers with complementary outputs (all I/O Banks) Types of Output Buffers Differential Output  All I/O Banks Emulation Capability PCI Support No Table 2-9. Supported Input Standards Input Standard ...

  • Page 21

    ... Lattice Semiconductor Table 2-10. Supported Output Standards Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain 3 PCI33 Differential Interfaces 1, 2 LVDS 2 BLVDS, RSDS 2 LVPECL 1. MachXO1200 and MachXO2280 devices have dedicated LVDS buffers. ...

  • Page 22

    ... Lattice Semiconductor Figure 2-18. MachXO2280 Banks V CCIO7 GND V CCIO6 GND Figure 2-19. MachXO1200 Banks V CCIO7 GND V CCIO6 GND Bank 0 Bank Bank 5 Bank Bank 0 Bank Bank 5 Bank 2-19 Architecture ...

  • Page 23

    ... Lattice Semiconductor Figure 2-20. MachXO640 Banks V CCO3 GND Figure 2-21. MachXO256 Banks GND V CCO1 Hot Socketing The MachXO devices have been carefully designed to ensure predictable behavior during power-up and power- down. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of ...

  • Page 24

    ... Lattice Semiconductor the system. These capabilities make the MachXO ideal for many multiple power supply and hot-swap applica- tions. Sleep Mode The MachXO “C” devices (V = 1.8/2.5/3.3V) have a sleep mode that allows standby current to be reduced dra- CC matically during periods of system inactivity. Entry and exit to Sleep mode is controlled by the SLEEPN pin. ...

  • Page 25

    ... I/Os as high, low, tristated or held at current value. This provides excellent flexibility for implementing systems where reconfiguration or reprogramming occurs on-the-fly. TransFR (Transparent Field Reconfiguration) TransFR (TFR unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a single ispVM command. See TN1087, tion Using TransFR Technology for details ...

  • Page 26

    ... Lattice Semiconductor Figure 2-22. MachXO Configuration and Programming Port Background Mode Program in seconds Non-Volatile Memory Space Density Shifting The MachXO family has been designed to enable density migration in the same package. Furthermore, the archi- tecture ensures a high success rate when performing design migration from lower density parts to higher density parts ...

  • Page 27

    ... PU © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com MachXO Family Data Sheet ...

  • Page 28

    ... Lattice Semiconductor MachXO1200 and MachXO2280 Hot Socketing Specifications Symbol Parameter Non-LVDS General Purpose sysIOs I Input or I/O Leakage Current DK LVDS General Purpose sysIOs I Input or I/O Leakage Current DK_LVDS 1. Insensitive to sequence CC, CCAUX,     (MAX CCIO CCIO 3 ...

  • Page 29

    ... LCMXO640C LCMXO1200C LCMXO2280C 4 All LCMXO ‘C’ Devices Over Recommended Operating Conditions Device LCMXO256C LCMXO640C LCMXO1200C LCMXO2280C LCMXO256E LCMXO640E LCMXO1200E LCMXO2280E LCMXO256E/C LCMXO640E/C LCMXO1200E/C LCMXO2280E/C 6 All devices 3-3 DC and Switching Characteristics MachXO Family Data Sheet 3 Typ. Max ...

  • Page 30

    ... J 6. Per Bank 2.5V. Does not include pull-up/pull-down. CCIO Over Recommended Operating Conditions Device LCMXO256C LCMXO640C LCMXO1200C LCMXO2280C LCMXO256E LCMXO640E LCMXO1200E LCMXO2280E LCMXO256E/C LCMXO640E/C LCMXO1200E/C LCMXO2280E/C 6 All devices or GND. 3-4 DC and Switching Characteristics MachXO Family Data Sheet 5 Typ ...

  • Page 31

    ... JTAG programming is at 25MHz 25°C, power supplies at nominal voltage Per Bank 2.5V. Does not include pull-up/pull-down. CCIO Device LCMXO256C LCMXO640C LCMXO1200C LCMXO2280C LCMXO256E LCMXO640E LCMXO1200E LCMXO2280E LCMXO256C/E LCMXO640C/E LCMXO1200/E LCMXO2280C/E 6 All devices or GND. 3-5 DC and Switching Characteristics MachXO Family Data Sheet ...

  • Page 32

    ... Lattice Semiconductor sysIO Recommended Operating Conditions Standard LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 LVTTL 3 PCI 1, 2 LVDS 1 LVPECL 1 BLVDS 1 RSDS 1. Inputs on chip. Outputs are implemented with the addition of external resistors. 2. MachXO1200 and MachXO2280 devices have dedicated LVDS buffers 3. Input on the top bank of the MachXO1200 and MachXO2280 only. ...

  • Page 33

    ... Lattice Semiconductor sysIO Single-Ended DC Electrical Characteristics V IL Input/Output Standard Min. (V) Max. (V) LVCMOS 3.3 -0.3 0.8 LVTTL -0.3 0.8 LVCMOS 2.5 -0.3 0.7 LVCMOS 1.8 -0.3 0.35V CCIO LVCMOS 1.5 -0.3 0.35V CCIO LVCMOS 1.2 -0.3 0.42 (“C” Version) LVCMOS 1.2 -0.3 0.35V (“E” Version) PCI -0.3 0.3V CCIO 1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O Bank and the end of an I/O Bank, as shown in the logic signal connections table shall not exceed n * 8mA ...

  • Page 34

    ... Lattice Semiconductor sysIO Differential Electrical Characteristics LVDS Parameter Symbol Parameter Description V V Input Voltage INP, INM V Differential Input Threshold THD V Input Common Mode Voltage CM I Input current IN V Output high voltage for Output low voltage for Output voltage differential ...

  • Page 35

    ... Lattice Semiconductor Table 3-1. LVDS DC Conditions Parameter Z Output impedance OUT R Driver series resistor S R Driver parallel resistor P R Receiver termination T V Output high voltage OH V Output low voltage OL V Output differential voltage OD V Output common mode voltage CM Z Back impedance BACK I DC output current ...

  • Page 36

    ... Lattice Semiconductor Table 3-2. BLVDS DC Conditions Symbol Z OUT R TLEFT R TRIGHT For input buffer, see LVDS table. LVPECL The MachXO family supports the differential LVPECL standard through emulation. This output standard is emu- lated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs on all the devices ...

  • Page 37

    ... Lattice Semiconductor For further information on LVPECL, BLVDS and other differential interfaces please see details of additional techni- cal documentation at the end of the data sheet. RSDS The MachXO family supports the differential RSDS standard. The output standard is emulated using complemen- tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs on all the devices. The RSDS input standard is supported by the LVDS differential input buffer on certain devices ...

  • Page 38

    ... Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst case numbers in the operating range. Actual delays may be much faster. The ispLEVER design tool from Lattice can provide logic timing numbers at a particular temperature and voltage. ...

  • Page 39

    ... Lattice Semiconductor MachXO External Switching Characteristics Parameter Description General I/O Pin Parameters (Using Global Clock without PLL) t Best Case t Through 1 LUT Best Case Clock to Output - From PFU CO t Clock to Data Setup - To PFU SU t Clock to Data Hold - To PFU H f Clock Frequency of I/O and PFU Register ...

  • Page 40

    ... Lattice Semiconductor MachXO Internal Timing Parameters Parameter Description PFU/PFF Logic Mode Timing t LUT4 delay ( inputs to F output) LUT4_PFU t LUT6 delay ( inputs to OFX output) LUT6_PFU t Set/Reset to output of PFU LSR_PFU t Clock to Mux (M0,M1) input setup time SUM_PFU t Clock to Mux (M0,M1) input hold time ...

  • Page 41

    ... Lattice Semiconductor MachXO Family Timing Adders Buffer Type Input Adjusters 4 LVDS25 LVDS 4 BLVDS25 BLVDS 4 LVPECL33 LVPECL LVTTL33 LVTTL LVCMOS33 LVCMOS 3.3 LVCMOS25 LVCMOS 2.5 LVCMOS18 LVCMOS 1.8 LVCMOS15 LVCMOS 1.5 LVCMOS12 LVCMOS 1.2 4 PCI33 PCI Output Adjusters LVDS25E LVDS 2 LVDS25 LVDS 2.5 BLVDS25 BLVDS 2.5 LVPECL33 LVPECL 3.3 ...

  • Page 42

    ... Lattice Semiconductor sysCLOCK PLL Timing Parameter Descriptions f Input Clock Frequency (CLKI, CLKFB Output Clock Frequency (CLKOP, CLKOS) OUT f K-Divider Output Frequency (CLKOK) OUT2 f PLL VCO Frequency VCO f Phase Detector Input Frequency PFD AC Characteristics t Output Clock Duty Cycle Output Phase Accuracy ...

  • Page 43

    ... Lattice Semiconductor I/O SLEEPN Flash Download Time Symbol Minimum CCAUX t (later of the two supplies) REFRESH to Device I/O Active JTAG Port Timing Specifications Symbol f TCK [BSCAN] clock frequency MAX t TCK [BSCAN] clock pulse width BTCP t TCK [BSCAN] clock pulse width high BTCPH ...

  • Page 44

    ... Lattice Semiconductor Figure 3-5. JTAG Port Timing Waveforms TMS TDI TCK TDO Data to be captured from I/O Data to be driven out to I BTS BTH t t BTCPL BTCPH t t BTCO BTCOEN BTCRH t BTCRS Data Captured t t BTUPOEN ...

  • Page 45

    ... Lattice Semiconductor Switching Test Conditions Figure 3-6 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Figure 3-5. Figure 3-6. Output Test Load, LVTTL and LVCMOS Standards Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces Test Condition LVTTL and LVCMOS settings (L -> ...

  • Page 46

    ... Applies to MachXO “C” devices only. NC for “E” devices. © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

  • Page 47

    ... Lattice Semiconductor Pin Information Summary Pin Type 100 TQFP Single Ended User I/O 1 Differential Pair User I/O Muxed TAP Dedicated (Total Without Supplies) VCC VCCAUX Bank0 Bank1 VCCIO Bank2 Bank3 GND NC Bank0 Bank1 Single Ended/Differential I/O per Bank Bank2 Bank3 1. These devices support emulated LVDS outputs.þLVDS inputs are not supported. ...

  • Page 48

    ... Lattice Semiconductor Power Supply and NC Signal 100 TQFP VCC LCMXO256/640: 35, 90 LCMXO1200/2280: 17, 35, 66, 91 VCCIO0 LCMXO256: 60, 74, 92 LCMXO640: 80, 92 LCMXO1200/2280: 94 VCCIO1 LCMXO256: 10, 24, 41 LCMXO640: 60, 74 LCMXO1200/2280: 80 VCCIO2 LCMXO256: None LCMXO640: 29, 41 LCMXO1200/2280: 70 VCCIO3 LCMXO256: None LCMXO640: 10, 24 LCMXO1200/2280: 56 VCCIO4 LCMXO256/640: None ...

  • Page 49

    ... Lattice Semiconductor Power Supply and NC (Cont.) Signal 132 csBGA VCC H3, P6, G12, C7 VCCIO0 LCMXO640: B11, C5 LCMXO1200/2280: C5 VCCIO1 LCMXO640: L12, E12 LCMXO1200/2280: B11 VCCIO2 LCMXO640: N2, M10 LCMXO1200/2280: E12 LCMXO640: D2, K3  VCCIO3 LCMXO1200/2280: L12 VCCIO4 LCMXO640: None LCMXO1200/2280: M10 VCCIO5 LCMXO640: None ...

  • Page 50

    ... Lattice Semiconductor LCMXO256 and LCMXO640 Logic Signal Connections: 100 TQFP LCMXO256 Ball Pin Number Function Bank 1 PL2A 1 2 PL2B 1 3 PL3A 1 4 PL3B 1 5 PL3C 1 6 PL3D 1 7 PL4A 1 8 PL4B 1 9 PL5A 1 10 VCCIO1 1 11 PL5B 1 12 GNDIO1 1 13 PL5C ...

  • Page 51

    ... Lattice Semiconductor LCMXO256 and LCMXO640 Logic Signal Connections: 100 TQFP (Cont.) LCMXO256 Ball Pin Number Function Bank 43 PB4A 1 44 PB4B 1 45 PB4C 1 46 PB4D 1 47 PB5A 1 48* SLEEPN - 49 PB5C 1 50 PB5D 1 51 PR9B 0 52 PR9A 0 53 PR8B 0 54 PR8A 0 55 PR7D ...

  • Page 52

    ... Lattice Semiconductor LCMXO256 and LCMXO640 Logic Signal Connections: 100 TQFP (Cont.) LCMXO256 Ball Pin Number Function Bank 85 PT4B 0 86 PT4A 0 87 PT3D 0 88 VCCAUX - 89 PT3C 0 90 VCC - 91 PT3B 0 92 VCCIO0 0 93 GNDIO0 0 94 PT3A 0 95 PT2F 0 96 PT2E 0 97 PT2D 0 98 ...

  • Page 53

    ... Lattice Semiconductor LCMXO1200 and LCMXO2280 Logic Signal Connections: 100 TQFP LCMXO1200 Pin Ball Number Function Bank 1 PL2A 7 2 PL2B 7 3 PL3C 7 4 PL3D 7 5 PL4B 7 6 VCCIO7 7 7 PL6A 7 8 PL6B 7 9 GND - 10 PL7C 7 11 PL7D 7 12 PL8C 7 13 PL8D 7 14 ...

  • Page 54

    ... Lattice Semiconductor LCMXO1200 and LCMXO2280 Logic Signal Connections: 100 TQFP (Cont.) LCMXO1200 Pin Ball Number Function Bank 42 PB9A 4 43 PB9B 4 44 VCCIO4 4 45 PB10A 4 46 PB10B 4 47*** SLEEPN - 48 PB11A 4 49 PB11B 4 GNDIO3 50** - GNDIO4 51 PR16B 3 52 PR15B 3 53 PR15A 3 54 PR14B 3 55 ...

  • Page 55

    ... Lattice Semiconductor LCMXO1200 and LCMXO2280 Logic Signal Connections: 100 TQFP (Cont.) LCMXO1200 Pin Ball Number Function Bank 82 PT9A 1 83 GND - 84 PT8B 1 85 PT8A 1 86 PT7D 1 87 PT6F 0 88 PT6D 0 89 PT6C 0 90 VCCAUX - 91 VCC - 92 PT5B 0 93 PT4B 0 94 VCCIO0 0 95 PT3D ...

  • Page 56

    ... Lattice Semiconductor LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA LCMXO256 Ball Ball Number Function Bank B1 PL2A 1 C1 PL2B 1 D2 PL3A 1 D1 PL3B 1 C2 PL3C 1 E1 PL3D 1 E2 PL4A 1 F1 PL4B 1 F2 PL5A 1 G2 PL5B 1 H1 GNDIO1 1 H2 PL5C 1 J1 PL5D ...

  • Page 57

    ... Lattice Semiconductor LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA (Cont.) LCMXO256 Ball Ball Number Function Bank P13 PB5A 1 M12* SLEEPN - P14 PB5C 1 N13 PB5D 1 N14 PR9B 0 M14 PR9A 0 L13 PR8B 0 L14 PR8A 0 M13 PR7D 0 K14 PR7C 0 K13 PR7B 0 J14 PR7A ...

  • Page 58

    ... Lattice Semiconductor LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA (Cont.) LCMXO256 Ball Ball Number Function Bank A4 GNDIO0 0 B4 PT3A 0 A3 PT2F 0 B3 PT2E 0 A2 PT2D 0 C3 PT2C 0 A1 PT2B 0 B2 PT2A 0 N9 GND - B9 GND - B5 VCCIO0 0 A14 VCCIO0 0 H14 VCCIO0 0 P10 ...

  • Page 59

    ... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections:  132 csBGA LCMXO640 Ball Dual Ball # Function Bank Function Differential Ball # B1 PL2A PL2B PL2C PL2D PL3A PL3B PL3D 3 E1 GNDIO3 3 E2 PL5A PL5B 3 GSRN ...

  • Page 60

    ... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections:  132 csBGA (Cont.) LCMXO640 Ball Dual Ball # Function Bank Function Differential Ball # M9 PB7B 2 C N10 PB7E 2 T P10 PB7F 2 C N11 GNDIO2 2 P11 PB8C 2 T M11 PB8D 2 C P12 PB9C 2 T P13 ...

  • Page 61

    ... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections:  132 csBGA (Cont.) LCMXO640 Ball Dual Ball # Function Bank Function Differential Ball # B9 PT7B PT7A PT6B 0 PCLK0_1*** C B8 PT6A PT5B 0 PCLK0_0*** C B7 PT5A VCCAUX - C7 VCC - A6 PT4D PT4C ...

  • Page 62

    ... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections:  144 TQFP LCMXO640 Pin Ball Dual Number Function Bank Function Differential 1 PL2A 3 2 PL2C 3 3 PL2B 3 4 PL3A 3 5 PL2D 3 6 PL3B 3 7 PL3C 3 8 PL3D 3 9 PL4A 3 10 VCCIO3 3 11 ...

  • Page 63

    ... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections:  144 TQFP (Cont.) LCMXO640 Pin Ball Dual Number Function Bank Function Differential 51 TDI 2 TDI 52 VCC - 53 VCCAUX - 54 PB5A 2 55 PB5B 2 PCLKT2_1*** 56 PB5D 2 57 PB6A 2 58 PB6B 2 PCLKT2_0*** 59 GND - 60 PB7C 2 61 PB7E 2 62 ...

  • Page 64

    ... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections:  144 TQFP (Cont.) LCMXO640 Pin Ball Dual Number Function Bank Function Differential 101 PR3D 1 102 PR3C 1 103 PR3B 1 104 PR2D 1 105 PR3A 1 106 PR2B 1 107 PR2C 1 108 PR2A 1 109 PT9F 0 110 ...

  • Page 65

    ... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA LCMXO640 Ball Ball Dual Number Function Bank Function Differential GND GNDIO3 3 VCCIO3 VCCIO3 PL3A PL3B PL2C PL2D ...

  • Page 66

    ... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA (Cont.) LCMXO640 Ball Ball Dual Number Function Bank Function Differential J4 PL8A PL8B PL11A PL11B PL10C PL10D PL11C ...

  • Page 67

    ... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA (Cont.) LCMXO640 Ball Ball Dual Number Function Bank Function Differential - - - - M10 PB6A PB6C 2 T R10 PB6D 2 C T10 PB7C 2 T T11 PB7D 2 C N10 NC N11 NC VCCIO2 ...

  • Page 68

    ... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA (Cont.) LCMXO640 Ball Ball Dual Number Function Bank Function Differential J13 PR8C 1 T GND GND - K14 PR8B 1 C J14 PR8A 1 T K15 PR7D 1 C J15 PR7C ...

  • Page 69

    ... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA (Cont.) LCMXO640 Ball Ball Dual Number Function Bank Function Differential E11 NC E10 NC D12 PT9D 0 C D11 PT9C 0 T A14 PT7F 0 C A13 PT7E 0 T C12 PT8B 0 C C11 ...

  • Page 70

    ... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA (Cont.) LCMXO640 Ball Ball Dual Number Function Bank Function Differential PT2B PT2A VCCIO0 VCCIO0 0 GND GNDIO0 0 A1 GND - A16 GND - F11 GND ...

  • Page 71

    ... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA Ball Number Ball Function GND GNDIO7 VCCIO7 VCCIO7 D4 PL2A F5 PL2B B3 PL3A C3 PL3B E4 PL3C G6 PL3D A1 PL4A B1 PL4B F4 PL4C VCC VCC E3 PL4D D2 PL5A D3 PL5B G5 PL5C F3 PL5D C2 PL6A VCCIO7 VCCIO7 GND GNDIO7 C1 PL6B H5 PL6C G4 PL6D E2 PL7A ...

  • Page 72

    ... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function G2 PL11A H2 PL11B L3 PL11C L5 PL11D H1 PL12A VCCIO6 VCCIO6 GND GNDIO6 J2 PL12B L4 PL12C L6 PL12D K2 PL13A K1 PL13B J1 PL13C VCC VCC L2 PL13D M5 PL14D M3 PL14C L1 PL14B M2 PL14A M1 PL15A N1 PL15B M6 PL15C M4 PL15D VCCIO6 VCCIO6 ...

  • Page 73

    ... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function T2 PL20B P6 TMS V1 PB2A U2 PB2B T3 PB2C N7 TCK R4 PB2D R5 PB3A T4 PB3B VCC VCC R6 PB3C P7 PB3D U3 PB4A T5 PB4B V2 PB4C N8 TDO V3 PB4D T6 PB5A GND GNDIO5 VCCIO5 VCCIO5 U4 PB5B P8 PB5C T7 PB5D V4 TDI R8 PB6A ...

  • Page 74

    ... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function V10 PB9B N10 PB9C R10 PB9D P10 PB10F T10 PB10E U10 PB10D V11 PB10C U11 PB10B VCCIO4 VCCIO4 GND GNDIO4 T11 PB10A U12 PB11A R11 PB11B GND GND ...

  • Page 75

    ... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function GND GNDIO3 VCCIO3 VCCIO3 P15 PR20B N14 PR20A N15 PR19B M13 PR19A R15 PR18B T16 PR18A N16 PR17D M14 PR17C U17 PR17B VCC VCC U18 PR17A R17 PR16D ...

  • Page 76

    ... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function J13 PR10C M18 PR10B L18 PR10A GND GNDIO2 VCCIO2 VCCIO2 H16 PR9D H14 PR9C K18 PR9B J18 PR9A J17 PR8D VCC VCC H18 PR8C H17 PR8B G17 PR8A ...

  • Page 77

    ... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function E13 PT16D C15 PT16C F13 PT16B D14 PT16A A18 PT15D B17 PT15C A16 PT15B A17 PT15A VCC VCC D13 PT14D F12 PT14C C14 PT14B E12 PT14A C13 PT13D ...

  • Page 78

    ... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function A10 PT8E VCCIO0 VCCIO0 GND GNDIO0 A9 PT8D C9 PT8C B9 PT8B F9 VCCAUX A8 PT8A B8 PT7D C8 PT7C VCC VCC A7 PT7B B7 PT7A A6 PT6A B6 PT6B D8 PT6C F8 PT6D C7 PT6E E8 PT6F D7 PT5D VCCIO0 VCCIO0 GND GNDIO0 ...

  • Page 79

    ... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function F16 GND H10 GND H11 GND H8 GND H9 GND J10 GND J11 GND J4 GND J8 GND J9 GND K10 GND K11 GND K17 GND K8 GND K9 GND L10 GND L11 GND L8 GND ...

  • Page 80

    ... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function G8 VCCIO0 G7 VCCIO0 * Supports true LVDS outputs for “E” devices. *** Primary clock inputs are single-ended. MachXO Family Data Sheet LCMXO2280 Bank Dual Function 0 0 4-35 Pinout Information Differential ...

  • Page 81

    ... For further information regarding Thermal Management, refer to the following: • Thermal Management document • TN1090 - Power Estimation and Management for MachXO Devices • Power Calculator tool included with the Lattice ispLEVER design tool standalone download from  www.latticesemi.com/software MachXO Family Data Sheet Thermal Management document to find the device/package 4-36 ...

  • Page 82

    ... Note: MachXO devices are dual marked except the slowest commercial speed grade device.þFor example the commercial speed grade LCMXO640E-4F256C is also marked with industrial grade -3I grade.þThe slowest com- mercial speed grade does not have industrial markings.þ The markings appears as follows: © ...

  • Page 83

    ... Lattice Semiconductor Conventional Packaging Part Number LUTs LCMXO256C-3T100C 256 LCMXO256C-4T100C 256 LCMXO256C-5T100C 256 LCMXO256C-3M100C 256 LCMXO256C-4M100C 256 LCMXO256C-5M100C 256 Part Number LUTs LCMXO640C-3T100C 640 LCMXO640C-4T100C 640 LCMXO640C-5T100C 640 LCMXO640C-3M100C 640 LCMXO640C-4M100C 640 LCMXO640C-5M100C 640 LCMXO640C-3T144C 640 LCMXO640C-4T144C 640 LCMXO640C-5T144C 640 LCMXO640C-3M132C ...

  • Page 84

    ... LCMXO640E-3T100C 640 LCMXO640E-4T100C 640 LCMXO640E-5T100C 640 LCMXO640E-3M100C 640 LCMXO640E-4M100C 640 LCMXO640E-5M100C 640 LCMXO640E-3T144C 640 LCMXO640E-4T144C 640 LCMXO640E-5T144C 640 LCMXO640E-3M132C 640 LCMXO640E-4M132C 640 LCMXO640E-5M132C 640 LCMXO640E-3B256C 640 LCMXO640E-4B256C 640 LCMXO640E-5B256C 640 LCMXO640E-3FT256C 640 LCMXO640E-4FT256C 640 LCMXO640E-5FT256C 640 Supply Voltage I/Os Grade 1.8V/2.5V/3.3V 73 1.8V/2.5V/3.3V 73 1.8V/2.5V/3.3V 73 1.8V/2.5V/3.3V 113 1.8V/2.5V/3.3V 113 1 ...

  • Page 85

    ... Lattice Semiconductor Part Number LUTs LCMXO1200E-3T100C 1200 LCMXO1200E-4T100C 1200 LCMXO1200E-5T100C 1200 LCMXO1200E-3T144C 1200 LCMXO1200E-4T144C 1200 LCMXO1200E-5T144C 1200 LCMXO1200E-3M132C 1200 LCMXO1200E-4M132C 1200 LCMXO1200E-5M132C 1200 LCMXO1200E-3B256C 1200 LCMXO1200E-4B256C 1200 LCMXO1200E-5B256C 1200 LCMXO1200E-3FT256C 1200 LCMXO1200E-4FT256C 1200 LCMXO1200E-5FT256C 1200 Part Number LUTs LCMXO2280E-3T100C 2280 LCMXO2280E-4T100C ...

  • Page 86

    ... Lattice Semiconductor Conventional Packaging Part Number LUTs LCMXO256C-3T100I 256 LCMXO256C-4T100I 256 LCMXO256C-3M100I 256 LCMXO256C-4M100I 256 Part Number LUTs LCMXO640C-3T100I 640 LCMXO640C-4T100I 640 LCMXO640C-3M100I 640 LCMXO640C-4M100I 640 LCMXO640C-3T144I 640 LCMXO640C-4T144I 640 LCMXO640C-3M132I 640 LCMXO640C-4M132I 640 LCMXO640C-3B256I 640 LCMXO640C-4B256I 640 LCMXO640C-3FT256I 640 LCMXO640C-4FT256I ...

  • Page 87

    ... Part Number LUTs LCMXO640E-3T100I 640 LCMXO640E-4T100I 640 LCMXO640E-3M100I 640 LCMXO640E-4M100I 640 LCMXO640E-3T144I 640 LCMXO640E-4T144I 640 LCMXO640E-3M132I 640 LCMXO640E-4M132I 640 LCMXO640E-3B256I 640 LCMXO640E-4B256I 640 LCMXO640E-3FT256I 640 LCMXO640E-4FT256I 640 Part Number LUTs LCMXO1200E-3T100I 1200 LCMXO1200E-4T100I 1200 LCMXO1200E-3T144I 1200 LCMXO1200E-4T144I 1200 LCMXO1200E-3M132I 1200 ...

  • Page 88

    ... Lattice Semiconductor Lead-Free Packaging Part Number LUTs LCMXO256C-3TN100C 256 LCMXO256C-4TN100C 256 LCMXO256C-5TN100C 256 LCMXO256C-3MN100C 256 LCMXO256C-4MN100C 256 LCMXO256C-5MN100C 256 Part Number LUTs LCMXO640C-3TN100C 640 LCMXO640C-4TN100C 640 LCMXO640C-5TN100C 640 LCMXO640C-3MN100C 640 LCMXO640C-4MN100C 640 LCMXO640C-5MN100C 640 LCMXO640C-3TN144C 640 LCMXO640C-4TN144C 640 LCMXO640C-5TN144C 640 LCMXO640C-3MN132C ...

  • Page 89

    ... LCMXO256E-5MN100C 256 Part Number LUTs LCMXO640E-3TN100C 640 LCMXO640E-4TN100C 640 LCMXO640E-5TN100C 640 LCMXO640E-3MN100C 640 LCMXO640E-4MN100C 640 LCMXO640E-5MN100C 640 LCMXO640E-3TN144C 640 LCMXO640E-4TN144C 640 LCMXO640E-5TN144C 640 LCMXO640E-3MN132C 640 LCMXO640E-4MN132C 640 LCMXO640E-5MN132C 640 LCMXO640E-3BN256C 640 LCMXO640E-4BN256C 640 LCMXO640E-5BN256C 640 LCMXO640E-3FTN256C 640 LCMXO640E-4FTN256C 640 LCMXO640E-5FTN256C 640 ...

  • Page 90

    ... Lattice Semiconductor Part Number LUTs LCMXO1200E-3TN100C 1200 LCMXO1200E-4TN100C 1200 LCMXO1200E-5TN100C 1200 LCMXO1200E-3TN144C 1200 LCMXO1200E-4TN144C 1200 LCMXO1200E-5TN144C 1200 LCMXO1200E-3MN132C 1200 LCMXO1200E-4MN132C 1200 LCMXO1200E-5MN132C 1200 LCMXO1200E-3BN256C 1200 LCMXO1200E-4BN256C 1200 LCMXO1200E-5BN256C 1200 LCMXO1200E-3FTN256C 1200 LCMXO1200E-4FTN256C 1200 LCMXO1200E-5FTN256C 1200 Part Number LUTs LCMXO2280E-3TN100C 2280 LCMXO2280E-4TN100C ...

  • Page 91

    ... Lattice Semiconductor Lead-Free Packaging Part Number LUTs LCMXO256C-3TN100I 256 LCMXO256C-4TN100I 256 LCMXO256C-3MN100I 256 LCMXO256C-4MN100I 256 Part Number LUTs LCMXO640C-3TN100I 640 LCMXO640C-4TN100I 640 LCMXO640C-3MN100I 640 LCMXO640C-4MN100I 640 LCMXO640C-3TN144I 640 LCMXO640C-4TN144I 640 LCMXO640C-3MN132I 640 LCMXO640C-4MN132I 640 LCMXO640C-3BN256I 640 LCMXO640C-4BN256I 640 LCMXO640C-3FTN256I 640 LCMXO640C-4FTN256I ...

  • Page 92

    ... Part Number LUTs LCMXO640E-3TN100I 640 LCMXO640E-4TN100I 640 LCMXO640E-3MN100I 640 LCMXO640E-4MN100I 640 LCMXO640E-3TN144I 640 LCMXO640E-4TN144I 640 LCMXO640E-3MN132I 640 LCMXO640E-4MN132I 640 LCMXO640E-3BN256I 640 LCMXO640E-4BN256I 640 LCMXO640E-3FTN256I 640 LCMXO640E-4FTN256I 640 Part Number LUTs LCMXO1200E-3TN100I 1200 LCMXO1200E-4TN100I 1200 LCMXO1200E-3TN144I 1200 LCMXO1200E-4TN144I 1200 LCMXO1200E-3MN132I 1200 ...

  • Page 93

    ... PCI: www.pcisig.com © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

  • Page 94

    ... April 2006 02.0 Architecture © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com ...

  • Page 95

    ... Lattice Semiconductor Date Version April 2006 02.0 Architecture (cont.) (cont.) DC and Switching Characteristics Pinout Information Ordering Information May 2006 02.1 Pinout Information August 2006 02.2 Section “Top View of the MachXO1200 Device” figure updated. (cont.) “Top View of the MachXO640 Device” figure updated. “Top View of the MachXO256 Device” figure updated. ...

  • Page 96

    ... Lattice Semiconductor Date Version November 2006 02.3 DC and Switching Characteristics December 2006 02.4 Architecture Pinout Information February 2007 02.5 Architecture August 2007 02.6 DC and Switching Characteristics November 2007 02.7 DC and Switching Characteristics Pinout Information Supplemental Information June 2009 02.8 Introduction Pinout Information Ordering Information July 2010 02.9 DC and Switching ...