530GC24M5760DG Silicon Labs, 530GC24M5760DG Datasheet

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530GC24M5760DG

Manufacturer Part Number
530GC24M5760DG
Description
Standard Clock Oscillators SINGLE XO 6 PIN 0.3PS RS JTR
Manufacturer
Silicon Labs
Datasheet

Specifications of 530GC24M5760DG

Product Category
Standard Clock Oscillators
Rohs
yes
Product
XO
Package / Case
7 mm x 5 mm
Frequency
24.576 MHz
Frequency Stability
20 PPM
Supply Voltage
2.5 V
Load Capacitance
15 pF
Termination Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Maximum Operating Temperature
+ 85 C
Output Format
CMOS
Dimensions
5 mm W x 7 mm L
Mounting Style
SMD/SMT
C
Features
Applications
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
Functional Block Diagram
Rev. 1.3 4/13
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
jitter performance
3x better frequency stability than
SAW-based oscillators
SONET/SDH
Networking
SD/HD video
R YS TA L
V
OE
DD
Frequency
Fixed
XO
O
SCILLATOR
®
with superior
10–1400 MHz
Synthesis
Any-rate
DSPLL
Clock
Copyright © 2013 by Silicon Laboratories
®
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
(XO) (10 M H
CLK–
GND
CLK+
®
circuitry
Z T O
S i530/ 531
Si530 (LVDS/LVPECL/CML)
Si531 (LVDS/LVPECL/CML)
GND
GND
GND
Ordering Information:
1 . 4 GH
NC
OE
OE
NC
OE
NC
Pin Assignments:
Si530 (CMOS)
See page 7.
See page 6.
1
2
3
1
2
3
1
2
3
Si5602
(Top View)
R
E V I S I O N
Z
6
5
4
6
5
4
6
5
4
)
V
CLK–
CLK+
V
NC
CLK
V
CLK–
CLK+
Si530/531
DD
DD
DD
D

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530GC24M5760DG Summary of contents

Page 1

SCILLATOR Features  Available with any-rate output frequencies from 10 MHz to 945 MHz and select frequencies to 1.4 GHz ®  3rd generation DSPLL with superior jitter performance  3x better frequency stability ...

Page 2

Si530/531 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter 1 Supply Voltage Supply Current 2 Output Enable (OE) Operating Temperature Range Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further ...

Page 3

Table 2. CLK± Output Frequency Characteristics (Continued) Parameter Total Stability 4 Powerup Time Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from ...

Page 4

Si530/531 Table 4. CLK± Output Phase Jitter Parameter Symbol 1 Phase Jitter (RMS) for F > 500 MHz OUT 1 Phase Jitter (RMS) for F of 125 to 500 MHz OUT Phase Jitter (RMS) for 160 ...

Page 5

Table 7. Environmental Compliance The Si530/531 meets the following qualification test requirements. Parameter Mechanical Shock Mechanical Vibration Solderability Gross & Fine Leak Resistance to Solder Heat Moisture Sensitivity Level Contact Pads Table 8. Thermal Characteristics (Typical values ...

Page 6

Si530/531 2. Pin Descriptions CLK– GND 3 4 CLK+ Si530 LVDS/LVPECL/CML Pin Symbol LVDS/LVPECL/CML Function 1 OE (CMOS only (LVPECL,LVDS clock output disabled (outputs tristated) CML ...

Page 7

Ordering Information The Si530/531 XO supports a variety of options including frequency, temperature stability, output format, and V Specific device configurations are programmed into the Si530/531 at time of shipment. Configurations can be specified using the Part Number Configuration ...

Page 8

Si530/531 4. Outline Diagram and Suggested Pad Layout Figure 2 illustrates the package details for the Si530/531. Table 12 lists the values for the dimensions shown in the illustration. Table 12. Package Diagram Dimensions (mm) Dimension ...

Page 9

Si530/Si531 Mark Specification Figure 3 illustrates the mark specification for the Si530/Si531. Table 13 lists the line information.   Table 13. Si53x Top Mark Description Line Position 1 1–10 “SiLabs"+ Part Family Number, 53x (First 3 characters in part ...

Page 10

Si530/531 6. 6-Pin PCB Land Pattern Figure 4 illustrates the 6-pin PCB land pattern for the Si530/531. Table 14 lists the values for the dimensions shown in the illustration. Figure 4. Si530/531 PCB Land Pattern Table 14. PCB Land Pattern ...

Page 11

OCUMENT HANGE IST Revision 0.4 to Revision 0.5  Updated Table 1, “Recommended Operating Conditions,” on page 2. Added maximum supply current specifications.  Specified relationship between temperature at startup  and operation temperature.  Updated Table ...

Page 12

... Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog- intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. ...

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