LCMXO2280E-5BN256C Lattice, LCMXO2280E-5BN256C Datasheet
LCMXO2280E-5BN256C
Specifications of LCMXO2280E-5BN256C
Available stocks
Related parts for LCMXO2280E-5BN256C
LCMXO2280E-5BN256C Summary of contents
Page 1
... MachXO2 Product Family Qualification Summary Lattice Document # 25 – 106923 February 2013 1 Lattice Semiconductor Corporation Doc. #25-106923 Rev. F ...
Page 2
... Industry standards for qualification of the technology and device packaging. This program ensures you only receive product that meets the most demanding requirements for Quality and Reliability. Your feedback is valuable to Lattice. If you have suggestions to improve this report, or the data included, we encourage you to contact your Lattice representative. ...
Page 3
... INDEX 1.0 INTRODUCTION .................................................................................................................................................. 4 Table 1.1 MachXO2 Product-Package 2.0 LATTICE PRODUCT QUALIFICATION PROGRAM .......................................................................................... 5 Figure 2.1: Lattice Standard Product Qualification Process Flow ............................................................................. 6 Table 2.2: Standard Qualification Testing ................................................................................................................. 8 3.0 QUALIFICATION DATA MACHXO2 PRODUCT FAMILY ................................................................................ 10 3.1 M XO2 ACH RODUCT AMILY IFE Table 3.1.1: MachXO2 Product Family Life Results ................................................................................................ 10 3.2 M XO2 ...
Page 4
... The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving 2.5x2.5 mm WLCSP to the 23x23 mm fpBGA. MachXO2 devices support density migration within the same package. INDEX Return Lattice Semiconductor Corporation Doc. #25-106923 Rev ...
Page 5
... LATTICE PRODUCT QUALIFICATION PROGRAM Lattice Semiconductor Corp. maintains a comprehensive reliability qualification program to assure that each product achieves its reliability goals. After initial qualification, the continued high reliability of Lattice products is assured through ongoing monitor programs as described in Lattice Semiconductor’s Reliability Monitor Program Procedure (Doc. #70-101667). All product qualification plans are generated in conformance with Lattice Semiconductor’ ...
Page 6
... Figure 2.1: Lattice Standard Product Qualification Process Flow This diagram represents the standard qualification flow used by Lattice to qualify new Product Families. The target end market for the Product Family determines which flow options are used. The MachXO2 Product Family was qualified using the Commercial / Industrial Qualification Option. ...
Page 7
... Room Temperature Post-stress testing & data logging INDEX Return Approved Qualification Plan Review Automotive Automotive or Commercial? Automotive 3-Temperature Pre-stress testing & data logging 3-Temperature Post-stress testing & data logging Qualification Failures? Failure Analysis Qualification Report 7 Lattice Semiconductor Corporation Doc. #25-106923 Rev. F ...
Page 8
... Plastic Packages only Design, Foundry Process, Package Qualification Design, Foundry Process, Package Qualification. This test is required only for Automotive-qualified devices with maximum rated power > 1 watt or DTJ > 40ºC. Foundry Process, Package Qualification Plastic Packages only Lattice Semiconductor Corporation Doc. #25-106923 Rev. F ...
Page 9
... C, 85% Relative Humidity Measure all dimensions 5 devices listed on the case outline. Per Package Type 3 devices per package / 30 balls each unit 9 PERFORMED ON Design, Foundry Process, Package Qualification Plastic Packages only Package Qualification Package Qualification Lattice Semiconductor Corporation Doc. #25-106923 Rev. F ...
Page 10
... JUNCTION 1000 Hrs 2000 Hrs Cumulative Result Result N/A N/A N/A N/A N N/A A N/A N/A N/A N/A N Lattice Semiconductor Corporation Doc. #25-106923 Rev. F Hours N/A N/A N/A 58,000 59,000 60,000 50,000 50,000 47,000 N/A N/A N/A 60,000 56,000 40,000 98,000 98,000 94,000 ...
Page 11
... Lattice Semiconductor Corporation Doc. #25-106923 Rev. F Cumulative Hours N/A N/A N/A 59,000 60,000 60,000 100,000 98,000 100,000 60,000 60,000 60,000 48,000 49,000 50,000 80,000 80,000 80,000 100,000 96,000 96,000 80,000 80,000 ...
Page 12
... TG144 LCMXO2-7000ZE TG144 * Qual lot #4 includes tunnel oxide (TOX) process splits: nominal, thick and thin TOX respectively. All passed qual. Note: A detailed MachXO2 Flash Data Retention report is available upon request. Lattice Semiconductor Corp. document #25-106925. INDEX Return =3.47V CCIO 168 Hrs ...
Page 13
... CYC CYC CYC Lattice Semiconductor Corporation Doc. #25-106923 Rev. F 100K CYC ...
Page 14
... LCMXO2- 4000ZE LCMXO2- 2000ZE LCMXO2- 1200ZE LCMXO2- 640ZE LCMXO2- HBM>2000V 256ZE Class 2* * The LCMXO2-256ZE HBM is JESD22-A114E Class 2 starting with die code revision B. See Lattice PCN-07A-12 for details. INDEX Return 100-TQFP 132-csBGA 144-TQFP 184csBGA (14x14mm, (8x8mm, (20x20mm, (8x8mm, 0.5mm 0.5mm 0.5mm ...
Page 15
... HBM>2000V HBM>2000V HBM>2000V HBM>2000V Class 2 Class 2 Class 2 Class 2 HBM>2000V HBM>2000V HBM>2000V HBM>2000V Class 2 Class 2 Class 2 Class 2 HBM>2000V HBM>2000V Class 2 Class 2 Lattice Semiconductor Corporation Doc. #25-106923 Rev. F ...
Page 16
... Lattice Semiconductor Corporation Doc. #25-106923 Rev. F ...
Page 17
... MachXO2 product family was tested per the JESD22-C101D, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components procedure and Lattice Procedure # 70-100844. All units were Class tested at room ambient prior to reliability stress and after reliability stress. No failures were observed within the passing classification ...
Page 18
... CDM>1kV CDM>1kV CDM>1kV CDM>1kV Class IV Class IV Class IV Class IV CDM>800V CDM>900V CDM>800V CDM>1kV Class III Class III Class III Class IV CDM>1kV CDM>1kV Class IV Class IV Lattice Semiconductor Corporation Doc. #25-106923 Rev. F ...
Page 19
... Latch-Up: MachXO2 product family was tested per the JEDEC EIA/JESD78A IC Latch-up Test procedure and Lattice Procedure # 70-101570. All units were Class tested at room ambient prior to reliability stress and after reliability stress. No failures were observed within the passing classification. Table 3.4.4 MachXO2 I/O Latch Up >100mA @ HOT (105°C) Data ...
Page 20
... Vcc > 1.5x Vcc > 1.5x Vcc > 1.5x Vcc Class II Class II Class II Class II > 1.5x Vcc > 1.5x Vcc > 1.5x Vcc > 1.5x Vcc Class II Class II Class II Class II > 1.5x Vcc > 1.5x Vcc Class II Class II Lattice Semiconductor Corporation Doc. #25-106923 Rev. F ...
Page 21
... Package Package Package not offered not offered not offered Package Package Package not offered not offered not offered INDEX Return Lattice Semiconductor Corporation Doc. #25-106923 Rev. F 1.0mm pitch) MSL3 1K cycles 264 hours 264 hours 1K hours Package not offered ...
Page 22
... Temperature Cycles, 24 hours bake @ 125°C, 30°C/60% RH, soak 192 hours, 260°C Reflow Simulation, 3 passes) performed before all package tests. MSL3 Packages: TQFP, μcBGA, csBGA, caBGA, ftBGA, fpBGA and QFN Method: Lattice Procedure # 70-103467, J-STD-020D.1 and JESD22-A113F Table 4.1.1 Surface Mount Precondition Data Product Name ...
Page 23
... Prior to Temperature Cycling testing, all devices are subjected to Surface Mount Preconditioning. MSL3 Packages: TQFP, csBGA, QFN Stress Duration: 1000 cycles Stress Conditions: Temperature cycling between -55°C to 125°C Method: Lattice Procedure # 70-101568 and JESD22-A104C, Condition B Table 4.2.1: Temperature Cycling Data Product Name Package ...
Page 24
... Lattice Semiconductor Corporation Doc. #25-106923 Rev. F Stress Duration 264 Hrs 264 Hrs 264 Hrs 264 Hrs 264 Hrs 264 Hrs 264 Hrs 264 Hrs 264 Hrs ...
Page 25
... Lattice Semiconductor Corporation Doc. #25-106923 Rev. F Stress Duration 96 Hrs 96 Hrs 96 Hrs 264 Hrs 264 Hrs 264 Hrs 264 Hrs 264 Hrs 264 Hrs 264 Hrs 264 Hrs ...
Page 26
... This is a relatively new requirement consistent with JESD47F for Pb-free, wirebonded packages. MSL3 Packages: TQFP, csBGA, QFN Stress Duration: 168, 500, 1000, 1500 hours. Temperature: 150°C (ambient) Method: Lattice Document # 87-101925 and JESD22-A103C / JESD22-A117A Table 4.5.1: MachXO2 High Temperature Storage Life Results Product Name Package ...
Page 27
... TTF 3 lots>380 yr SM Device Intermediate delta R +100% Celsius 100 TTF 3 lots>2400 yr Note: Reliability life times are based on listed temperature and use conditions. A Detailed WLR report is available upon request. Lattice Semiconductor Corporation document #73-106883. LVP MVN MVP -10% -10% -10 ...
Page 28
... Alpha Particle * The EBR SER data was taken on the ECP3. The ECP3 shares the same base technology and SRAM cell. Note: Detailed MachXO2 and ECP3 SER reports are available upon request. Lattice Semiconductor Corporation documents #25-106920 and #25-106669 respectively. INDEX Return ...
Page 29
... Ablebond 3230 Ablebond 2100A Hitachi Hitachi CEL9510HF10 9750HF10AKLU Gold (Au) Gold (Au) Thermosonic Ball Thermosonic Ball Bismaleimide n/a Triazine HL83X Series Matte Sn SAC305 Laser Laser Lattice Semiconductor Corporation Doc. #25-106923 Rev. F ...
Page 30
... Telephone: (503) 268-8000, FAX: (503) 268-8556 www.latticesemi.com © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice ...