LCMXO640E-5FN256C

Manufacturer Part NumberLCMXO640E-5FN256C
DescriptionCPLD - Complex Programmable Logic Devices Use LCMXO640E-5FTN25
ManufacturerLattice
LCMXO640E-5FN256C datasheet
 

Specifications of LCMXO640E-5FN256C

RohsyesMemory TypeSRAM
Number Of Macrocells320Maximum Operating Frequency600 MHz
Delay Time3.5 nsNumber Of Programmable I/os159
Operating Supply Voltage1.2 VMaximum Operating Temperature+ 85 C
Minimum Operating Temperature0 CPackage / CaseFPBGA
Mounting StyleSMD/SMTFactory Pack Quantity450
Supply Current14 mASupply Voltage - Max1.26 V
Supply Voltage - Min1.14 V  
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Lattice Semiconductor
of the devices also support differential input buffers. PCI clamps are available on the top Bank I/O buffers. The
PCI clamp is enabled after V
CC
figured.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
2. Left and Right sysIO Buffer Pairs
The sysIO buffer pairs in the left and right Banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (supporting ratioed and absolute input levels). The devices also have a
differential driver per output pair. The referenced input buffer can also be configured as a differential input buf-
fer. In these Banks the two pads in the pair are described as “true” and “comp”, where the true pad is associ-
ated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the
negative side of the differential I/O.
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when V
After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure
that all V
Banks are active with valid input logic levels to properly control the output logic states of all the I/O
CCIO
Banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a
weak pull-up to VCCIO. The I/O pins will maintain the blank configuration until VCC, VCCAUX and VCCIO have
reached satisfactory levels at which time the I/Os will take on the user-configured settings.
The V
and V
supply the power to the FPGA core fabric, whereas the V
CC
CCAUX
fers. In order to simplify system design while providing consistent and predictable I/O behavior, the I/O buffers
should be powered up along with the FPGA core fabric. Therefore, V
together with the V
and V
CC
CCAUX
Supported Standards
The MachXO sysIO buffer supports both single-ended and differential standards. Single-ended standards can be
further subdivided into LVCMOS and LVTTL. The buffer supports the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5, and 3.3V
standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength,
bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS and LVPECL
output emulation is supported on all devices. The MachXO1200 and MachXO2280 support on-chip LVDS output
buffers on approximately 50% of the I/Os on the left and right Banks. Differential receivers for LVDS, BLVDS and
LVPECL are supported on all Banks of MachXO1200 and MachXO2280 devices. PCI support is provided in the top
Banks of the MachXO1200 and MachXO2280 devices. Table 2-8 summarizes the I/O characteristics of the devices
in the MachXO family.
Tables 2-9 and 2-10 show the I/O standards (together with their supply and reference voltages) supported by the
MachXO devices. For further information on utilizing the sysIO buffer to support a variety of standards please see
the details of additional technical documentation at the end of this data sheet.
, V
, and V
are at valid operating levels and the device has been con-
CCAUX
CCIO
CC
supplies
2-16
Architecture
MachXO Family Data Sheet
and V
have reached satisfactory levels.
CCAUX
supplies power to the I/O buf-
CCIO
supplies should be powered up before or
CCIO