LCMXO640E-5FN256C

Manufacturer Part NumberLCMXO640E-5FN256C
DescriptionCPLD - Complex Programmable Logic Devices Use LCMXO640E-5FTN25
ManufacturerLattice
LCMXO640E-5FN256C datasheet
 

Specifications of LCMXO640E-5FN256C

RohsyesMemory TypeSRAM
Number Of Macrocells320Maximum Operating Frequency600 MHz
Delay Time3.5 nsNumber Of Programmable I/os159
Operating Supply Voltage1.2 VMaximum Operating Temperature+ 85 C
Minimum Operating Temperature0 CPackage / CaseFPBGA
Mounting StyleSMD/SMTFactory Pack Quantity450
Supply Current14 mASupply Voltage - Max1.26 V
Supply Voltage - Min1.14 V  
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Lattice Semiconductor
sysCLOCK PLL Timing
Parameter
Descriptions
f
Input Clock Frequency (CLKI, CLKFB)
IN
f
Output Clock Frequency (CLKOP, CLKOS)
OUT
f
K-Divider Output Frequency (CLKOK)
OUT2
f
PLL VCO Frequency
VCO
f
Phase Detector Input Frequency
PFD
AC Characteristics
t
Output Clock Duty Cycle
DT
4
t
Output Phase Accuracy
PH
1
t
Output Clock Period Jitter
OPJIT
t
Input Clock to Output Clock Skew
SK
t
Output Clock Pulse Width
W
2
t
PLL Lock-in Time
LOCK
t
Programmable Delay Unit
PA
t
Input Clock Period Jitter
IPJIT
t
External Feedback Delay
FBKDLY
t
Input Clock High Time
HI
t
Input Clock Low Time
LO
t
RST Pulse Width
RST
1. Jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock.
2. Output clock is valid after t
for PLL reset and dynamic delay adjustment.
LOCK
3. Using LVDS output buffers.
4. CLKOS as compared to CLKOP output.
5. When using an input frequency less than 25 MHz the output frequency must be less than or equal to 4 times the input frequency.
6. The on-chip oscillator can be used to provide reference clock input to the PLL provided the output frequency restriction for clock
inputs below 25 MHz are followed.
Rev. A 0.19
MachXO “C” Sleep Mode Timing
Symbol
Parameter
t
SLEEPN Low to Power Down
PWRDN
t
SLEEPN High to Power Up
PWRUP
t
SLEEPN Pulse Width
WSLEEPN
t
SLEEPN Pulse Rejection
WAWAKE
Rev. A 0.19
Over Recommended Operating Conditions
Conditions
Input Divider (M) = 1;
Feedback Divider (N) <= 4
Input Divider (M) = 1; 
Feedback Divider (N) <= 4
Default duty cycle selected
f
>= 100 MHz
OUT
f
< 100 MHz
OUT
Divider ratio = integer
At 90% or 10%
 100 MHz
f
OUT
f
< 100 MHz
OUT
90% to 90%
10% to 10%
Device
All
LCMXO256
LCMXO640
LCMXO1200
LCMXO2280
All
All
3-16
DC and Switching Characteristics
MachXO Family Data Sheet
Min.
Max.
Units
25
420
18
25
5, 6
25
420
0.195
210
420
840
25
18
25
5, 6
3
45
55
0.05
+/-120
0.02
+/-200
3
1
150
100
450
+/-200
0.02
10
0.5
0.5
10
Min.
Typ.
Max
400
400
600
800
1000
400
100
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
UI
ps
UIPP
ps
ns
µs
ps
ps
UI
ns
ns
ns
ns
Units
ns
µs
µs
µs
µs
ns
ns