LCMXO640E-5FN256C

Manufacturer Part NumberLCMXO640E-5FN256C
DescriptionCPLD - Complex Programmable Logic Devices Use LCMXO640E-5FTN25
ManufacturerLattice
LCMXO640E-5FN256C datasheet
 

Specifications of LCMXO640E-5FN256C

RohsyesMemory TypeSRAM
Number Of Macrocells320Maximum Operating Frequency600 MHz
Delay Time3.5 nsNumber Of Programmable I/os159
Operating Supply Voltage1.2 VMaximum Operating Temperature+ 85 C
Minimum Operating Temperature0 CPackage / CaseFPBGA
Mounting StyleSMD/SMTFactory Pack Quantity450
Supply Current14 mASupply Voltage - Max1.26 V
Supply Voltage - Min1.14 V  
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Lattice Semiconductor
Figure 2-6. Distributed Memory Primitives
SPR16x2
AD0
AD1
AD2
AD3
DI0
DI1
WRE
CK
ROM16x1
AD0
AD1
AD2
AD3
ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is
accomplished through the programming interface during configuration.
PFU Modes of Operation
Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the
functionality possible at the PFU level.
Table 2-4. PFU Modes of Operation
Logic
LUT 4x8 or
MUX 2x1 x 8
LUT 5x4 or
MUX 4x1 x 4
LUT 6x 2 or
MUX 8x1 x 2
LUT 7x1 or
MUX 16x1 x 1
Routing
There are many resources provided in the MachXO devices to route signals individually or as buses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-
ments.
The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2
(spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connec-
tions in the horizontal and vertical directions.
WAD0
WAD1
DO0
WAD2
WAD3
DO1
DI0
DI1
WCK
WRE
DO0
Ripple
RAM
SPR16x2 x 4
2-bit Add x 4
DPR16x2 x 2
SPR16x4 x 2
2-bit Sub x 4
DPR16x4 x 1
2-bit Counter x 4
SPR16x8 x 1
2-bit Comp x 4
2-6
Architecture
MachXO Family Data Sheet
DPR16x2
RAD0
RAD1
RAD2
RAD3
RDO0
RDO1
WDO0
WDO1
ROM
ROM16x1 x 8
ROM16x2 x 4
ROM16x4 x 2
ROM16x8 x 1