NB4N527SMNR2G ON Semiconductor, NB4N527SMNR2G Datasheet

IC DRVR/RCVR/BUFF/XLATOR 16-QFN

NB4N527SMNR2G

Manufacturer Part Number
NB4N527SMNR2G
Description
IC DRVR/RCVR/BUFF/XLATOR 16-QFN
Manufacturer
ON Semiconductor
Datasheet

Specifications of NB4N527SMNR2G

Logic Type
Receiver, Driver, Buffer, Translator
Supply Voltage
3.3V
Number Of Bits
2
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
NB4N527S
3.3V, 2.5Gb/s Dual
AnyLevel™ to LVDS
Receiver/Driver/Buffer/
Translator with Internal
Input Termination
capable of translating AnyLevel
HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the
distance, noise immunity of the system design, and transmission line
media, this device will receive, drive or translate data or clock signals
up to 2.5 Gb/s or 1.5 GHz, respectively.
GND + 50 mV to V
termination resistors is ideal for translating differential or
single−ended data or clock signals to 350 mV typical LVDS output
levels without use of any additional external components (Figure 6).
NB4N527S is targeted for data, wireless and telecom applications as
well as high speed logic interface where jitter and package size are
main requirements. Application notes, models, and support
documentation are available on www.onsemi.com.
© Semiconductor Components Industries, LLC, 2007
April, 2007 − Rev. 4
NB4N527S is a clock or data Receiver/Driver/Buffer/Translator
The NB4N527S has a wide input common mode range of
The device is offered in a small 3 mm x 3 mm QFN−16 package.
Maximum Input Clock Frequency up to 1.5 GHz
Maximum Input Data Rate up to 2.5 Gb/s (Figure 5)
470 ps Maximum Propagation Delay\
1 ps Maximum RMS Jitter
140 ps Maximum Rise/Fall Times
Single Power Supply; V
Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs
Internal 50 W Termination Resistor per Input Pin
GND + 50 mV to V
Pb−Free Packages are Available
PRBS 2
Figure 2. Typical Output Waveform at 2.488 Gb/s with
23−1
(V
CC
INPP
CC
− 50 mV combined with two 50 W internal
Device DDJ = 10 ps
− 50 mV V
= 400 mV; Input Signal DDJ = 14 ps)
CC
TIME (58 ps/div)
= 3.3 V $10%
TM
CMR
input signal (LVPECL, CML,
Range
1
*R
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
TIN
*For additional marking information, refer to
CASE 485G
MN SUFFIX
Figure 1. Functional Block Diagram
(Note: Microdot may be in either location)
Application Note AND8002/D.
QFN−16
VTD1
VTD1
VTD0
VTD0
1
D1
D1
D0
D0
ORDERING INFORMATION
A
L
Y
W
G
http://onsemi.com
50 W*
50 W*
50 W*
50 W*
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
1
DIAGRAM*
16
MARKING
ALYW G
NB4N
527S
G
NB4N527S/D
Q0
Q0
Q1
Q1

Related parts for NB4N527SMNR2G

NB4N527SMNR2G Summary of contents

Page 1

NB4N527S 3.3V, 2.5Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer/ Translator with Internal Input Termination NB4N527S is a clock or data Receiver/Driver/Buffer/Translator TM capable of translating AnyLevel HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system ...

Page 2

Table 1. PIN DESCRIPTION Pin Name 1 VTD1 2 D1 LVPECL, CML, LVDS, LVCMOS, LVTTL, HSTL 3 D1 LVPECL, CML, LVDS, LVCMOS, LVTTL, HSTL 4 VTD1 5 GND LVDS Output 10 Q1 ...

Page 3

Table 2. ATTRIBUTES Moisture Sensitivity (Note 2) Flammability Rating ESD Protection Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter V Positive Power Supply ...

Page 4

Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS Symbol I Power Supply Current (Note 8) CC DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 11, 12, 16, and 18) V Input Threshold Reference Voltage Range (Note Single−ended Input HIGH Voltage ...

Page 5

Table 5. AC CHARACTERISTICS V CC Symbol Characteristic V Output Voltage Amplitude (@ V OUTPP (Figure 4) f Maximum Operating Data Rate DATA t , Differential Input to Differential Output PLH t Propagation Delay PHL t Duty Cycle Skew (Note ...

Page 6

Figure 5. Typical Output Waveform at 2.488 Gb/s with PRBS 100 mV; Input Signal DDJ = 14 ps) INPP 1. 1. TDx V TDx Figure 6. Input ...

Page 7

V CC NB4N527S = TDx LVPECL Driver V TDx = − 2.0 V TDx TDx CC GND Figure 7. LVPECL Interface V CC NB4N527S ...

Page 8

LVDS Driver Device Figure 14. Typical LVDS Termination for Output Driver and Device Evaluation Figure 16. Differential Input Driven Single−Ended IHmax V thmax ...

Page 9

... ORDERING INFORMATION Device NB4N527SMN NB4N527SMNG NB4N527SMNR2 NB4N527SMNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NB4N527S Package QFN−16 QFN−16 (Pb−Free) QFN−16 QFN−16 (Pb−Free) http://onsemi ...

Page 10

... Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...

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