M4A3-128/64-10CAC Lattice, M4A3-128/64-10CAC Datasheet

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M4A3-128/64-10CAC

Manufacturer Part Number
M4A3-128/64-10CAC
Description
CPLD - Complex Programmable Logic Devices HI PERF E2CMOS PLD
Manufacturer
Lattice
Datasheet

Specifications of M4A3-128/64-10CAC

Product Category
CPLD - Complex Programmable Logic Devices
Memory Type
EEPROM
Number Of Macrocells
128
Maximum Operating Frequency
100 MHz
Delay Time
5 ns
Number Of Programmable I/os
400
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
CABGA-100-400
Mounting Style
SMD/SMT
Number Of Product Terms Per Macro
20
Factory Pack Quantity
920
Supply Voltage - Max
3.6 V
Supply Voltage - Min
3 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M4A3-128/64-10CAC
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
FEATURES
Publication# ISPM4A
Amendment/ 0
High-performance, E
Flexible architecture for rapid logic designs
— Excellent First-Time-Fit
— SpeedLocking
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
High speed
— 5.0ns t
— 182MHz f
32 to 512 macrocells; 32 to 768 registers
44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-Friendly
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
Advanced E
Lead-free package options
PD
2
Commercial and 7.5ns t
Rev: M
Issue Date: September 2006
CNT
CMOS process provides high-performance, cost-effective solutions
TM
performance for guaranteed fixed timing
2
CMOS 3.3-V & 5-V CPLD families
TM
and refit feature
ispMACH
High Performance E
In-System Programmable Logic
PD
Industrial
TM
inputs and I/Os
4A CPLD Family
2
CMOS
®

Related parts for M4A3-128/64-10CAC

M4A3-128/64-10CAC Summary of contents

Page 1

FEATURES 2 ◆ High-performance, E CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs TM — Excellent First-Time-Fit TM — SpeedLocking performance for guaranteed fixed timing — Central, input and output switch matrices for 100% routability ...

Page 2

... M4A5-96 M4A5-128 M4A5-192 96 128 192 5.5 5.5 6.0 167 167 160 4.0 4.0 4.5 3.5 3.5 3 Yes Yes Yes Yes Yes Yes ispMACH 4A Family M4A3-256 M4A3-384 M4A3-512 256 384 512 128/160/192 160/192 160/192/256 5.5 6.5 7.5 167 154 125 4.0 4.5 5.5 3.5 3.5 5.0 110/150 149/155 179 Yes Yes Yes Yes Yes Yes M4A5-256 256 128 6 ...

Page 3

... The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5- xxx) and 3.3-V (M4A3-xxx) operation. ispMACH 4A products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1) interface ...

Page 4

... PLCC 32+2 32+2 44-pin TQFP 32+2 32+2 48-pin TQFP 32+2 32+2 100-pin TQFP 100-pin PQFP 144-pin TQFP 208-pin PQFP 4 3.3 V Devices M4A3-96 M4A3-128 M4A3-192 48+8 64+6 64+6 64+6 96+16 96+ Devices M4A5-96 M4A5-128 M4A5-192 48+8 64+6 64+6 96+16 ispMACH 4A Family M4A3-256 M4A3-384 M4A3-512 128+14, 160 160 160 128+14, 192 192 192 128+14 192 256 M4A5-256 128+14 ...

Page 5

... Notes for ispMACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page). 2. Block clocks do not go to I/O cells in M4A(3,5)-32/32. 3. M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do not connect to the central switch matrix ...

Page 6

... Macrocells ◆ Output switch matrix ◆ I/O cells ◆ Input switch matrix ◆ Clock generator ◆ Notes: 1. M4A3-64/64 internal switch matrix functionality embedded in central switch matrix. 6 ispMACH 4A Devices M4A3-64/32, M4A5-64/32 M4A3-96/48, M4A5-96/48 M4A3-128/64, M4A5-128/64 M4A3-192/96, M4A5-192/96 M4A3-256/128, M4A5-256/128 M4A3-384 M4A3-512 2:1 Yes ...

Page 7

... M4A3-32/32 and M4A5-32/32 M4A3-64/32 and M4A5-64/32 M4A3-64/64 M4A3-96/48 and M4A5-96/48 M4A3-128/64 and M4A5-128/64 M4A3-192/96 and M4A5-192/96 M4A3-256/128 and M4A5-256/128 M4A3-256/160 and M4A3-256/192 M4A3-384 M4A3-512 Logic Allocator Within the logic allocator, product terms are allocated to macrocells in “product term clusters.” The availability and distribution of product term clusters are automatically considered by the software as it fits functions within a PAL block ...

Page 8

Table 6. Logic Allocator for All ispMACH 4A Devices (except M4A(3,5)-32/32) Output Macrocell Output Macrocell ...

Page 9

Basic cluster with XOR 0 d. Basic cluster routed away; single-product-term, active high Figure 3. Logic Allocator Configurations: Synchronous Mode a. Basic cluster with XOR 0 d. Basic cluster routed away; single-product-term, active high Figure 4. Logic Allocator Configurations: ...

Page 10

Macrocell The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization control. The macrocell has two fundamental modes: synchronous and asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the macrocell. Power-Up Reset ...

Page 11

The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality is defined in Table 8. Note that ...

Page 12

Configuration D-type Register T-type Register D-type Latch Note: 1. Polarity of CLK/LE can be programmed Although the macrocell shows only one input to the register, the XOR gate in the logic allocator allows the D-, T-type register to emulate J-K, ...

Page 13

A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing flexibility. In asynchronous mode (Figure 8), a single individual product term is provided for initialization. It can be selected to control reset or preset. ...

Page 14

Output Switch Matrix The output switch matrix allows macrocells to be connected to any of several I/O cells within a PAL block. This provides high flexibility in determining pinout and allows design changes to occur without effecting pinout. In ispMACH ...

Page 15

... Table 10. Output Switch Matrix Combinations for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio Macrocell M12, M13 M14, M15 I/O Cell I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192 Macrocell M0 I/O0 M1 I/O0 M2 I/O0 M3 I/O0 M4 I/O0 M5 I/O0 M6 I/O0 M7 I/O0 M8 I/O8 M9 I/O8 M10 I/O8 M11 I/O8 M12 I/O8 M13 I/O8 M14 I/O8 M15 I/O8 I/O Cell I/O0 M0 I/O1 M0 ...

Page 16

... Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192 Macrocell I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 Table 12. Output Switch Matrix Combinations for M4A(3,5)-32/32 Macrocell M0, M1, M2, M3, M4, M5, M6, M7 M8, M9, M10, M11, M12, M13, M14, M15 I/O Cell I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 Table 13 ...

Page 17

I/O Cell The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback path, and flip-flop (except ispMACH 4A devices with 1:1 macrocell-I/O cell ratio). An individual output enable product term is provided for each ...

Page 18

Input Switch Matrix The input switch matrix (Figures 12 and 13) optimizes routing of inputs to the central switch matrix. Without the input switch matrix, each input and feedback signal has only one way to enter the central switch matrix. ...

Page 19

PAL Block Clock Generation Each ispMACH 4A device has four clock pins that can also be used as inputs. These pins drive a clock generator in each PAL block (Figure 14). The clock generator provides four clock signals that can ...

Page 20

TIMING MODEL The primary focus of the ispMACH 4A timing model is to accurately represent the timing in a ispMACH 4A device, and at the same time, be easy to understand. This model accurately describes all combinatorial and ...

Page 21

... At power-up, the Bus-Friendly latches are reset to a logic level “1.” For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site. ...

Page 22

... For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site. POWER MANAGEMENT Each individual PAL block in ispMACH 4A devices features a programmable low-power mode, which results in power savings 50%. The signal speed paths in the low-power PAL block will be slower than those in the non-low-power PAL block ...

Page 23

... MACROCELL M9 M10 C10 MACROCELL M10 M11 O5 MACROCELL C11 M11 M12 C12 MACROCELL M12 M13 O6 C13 MACROCELL M13 M14 C14 MACROCELL M14 M15 O7 C15 MACROCELL M15 16 16 ispMACH 4A Family M4A3-384 M4A3-512 18 18 I/O0 I/O CELL I/O1 I/O CELL I/O2 I/O CELL I/O3 I/O CELL I/O4 I/O CELL I/O5 I/O CELL I/O6 I/O CELL I/O7 I/O CELL 23 ...

Page 24

... INPUT 32 SWITCH MATRIX Figure 17. PAL Block for ispMACH 4A Devices with 1:1 Macrocell-I/O Cell Ratio (except M4A (3,5)-32/32) 24 M4A3-256/160 M4A3-64/64 M4A3-256/192 CLOCK GENERATOR MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL M5 O5 ...

Page 25

INPUT 32 SWITCH MATRIX Figure 18. PAL Block for M4A (3,5)-32/32 CLK0/I0 CLK0/I1 CLOCK GENERATOR MACROCELL MACROCELL MACROCELL MACROCELL O3 M3 ...

Page 26

BLOCK DIAGRAM – M4A(3,5)-32/ Block A I/O8–I/O15 8 I/O Cells 8 Output Switch 8 Matrix Macrocells AND Logic Array and Logic Allocator 16 33 Central Switch Matrix ...

Page 27

BLOCK DIAGRAM – M4A(3,5)-64/ Block A I/O0–I/O7 8 I/O Cells 8 4 Output Switch Matrix Macrocells AND Logic Array AND ...

Page 28

... BLOCK DIAGRAM – M4A3-64/ AND Logic Array and Logic Allocator 4 4 AND Logic Array 4 and Logic Allocator Block A Block I/O Cells I/O Cells 16 16 Output Switch Output Switch Matrix Macrocells Macrocells AND Logic Array ...

Page 29

BLOCK DIAGRAM – M4A(3,5)-96/48 Clock Generator Clock Generator Clock Generator I2, I3, I6, I7 Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE CLK0/I0, CLK1/I1, CLK2/I4, CLK3/I5 ispMACH ...

Page 30

BLOCK DIAGRAM – M4A(3,5)-128/64 Clock Generator Clock Generator Clock Generator Clock Generator I2, I5 Input Switch Input Switch Matrix Matrix OE OE Input Switch Input Switch Matrix Matrix OE OE Input Switch Input Switch Matrix Matrix OE OE Input Switch ...

Page 31

BLOCK DIAGRAM – M4A(3,5)-192/96 Block B I/O88—I/O95 8 I/O Cells 8 4 Output Switch Matrix Macrocells AND Logic Array and Logic Allocator 24 34 Block C I/O8—I/O15 Block D I/O0—I/O7 ...

Page 32

BLOCK DIAGRAM – M4A(3,5)-256/128 Block B I/O8–I/O15 8 I/O Cells 8 4 Output Switch Matrix Macrocells AND Logic Array and Logic Allocator AND ...

Page 33

... BLOCK DIAGRAM – M4A3-256/160, M4A3-256/192 Block B 16 I/O Cells 16 4 Output Switch Matrix Macrocells AND Logic Array and Logic Allocator AND Logic Array 4 and Logic Allocator 16 Macrocells Output Switch Matrix 4 16 ...

Page 34

... BLOCK DIAGRAM – M4A3-384/160, M4A3-384/192 Block B 8 Detail A I/O Cells 8 4 Output Switch Matrix Macrocells AND Logic Array and Logic Allocator AND Logic Array 4 and Logic Allocator 16 Macrocells Output Switch Matrix 4 8 I/O Cells ...

Page 35

... BLOCK DIAGRAM - M4A3-512/160, M4A3-512/192, M4A3-512/256 Block B 8 Detail A I/O Cells 8 4 Output Switch Matrix Macrocells AND Logic Array and Logic Allocator AND Logic Array 4 and Logic Allocator 16 Macrocells Output Switch Matrix 4 8 I/O Cells ...

Page 36

ABSOLUTE MAXIMUM RATINGS M4A5 Storage Temperature -65°C to +150°C Ambient Temperature with Power Applied ...

Page 37

... ABSOLUTE MAXIMUM RATINGS M4A3 Storage Temperature -65°C to +150°C Ambient Temperature with Power Applied -55°C to +100°C Device Junction Temperature +130°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . . .-0 +4 Input Voltage . . . . . . . . . . . . . . . . . . . . . . . -0 6.0 V Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . 2000 V Latchup Current (T = -40°C to +85° 200 mA ...

Page 38

TIMING PARAMETERS OVER OPERATING RANGES Combinatorial Delay: Internal combinatorial propagation t PDi delay t Combinatorial propagation delay PD Registered Delays: Synchronous clock setup time, D-type t SS register Synchronous clock setup time, T-type t SST register Asynchronous clock ...

Page 39

TIMING PARAMETERS OVER OPERATING RANGES Input Register Delays with ZHT Option: t Input register setup time - ZHT SIRZ t Input register hold time - ZHT HIRZ Input Latch Delays with ZHT Option: t Input latch setup time ...

Page 40

... WIRH WIRL SIRS HIRS Notes: 1. See “Switching Test Circuit” document on the Literature Download page of the Lattice web site. 2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 1 CAPACITANCE Parameter Symbol Parameter Description C ...

Page 41

I vs. FREQUENCY CC These curves represent the typical power consumption for a particular device at system frequency. The selected “typical” pattern is a 16-bit up-down counter. This pattern fills the device and exercises every macrocell. Maximum frequency shown uses ...

Page 42

PLCC CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32) Top View M4A(3,5)-64 I/O7 TDI CLK0/I0 M4A(3,5)-32/32 GND TCK I/O9 A10 B2 I/O10 A11 B3 I/O11 M4A(3,5)-64/32 PIN DESIGNATIONS CLK/I ...

Page 43

TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32) Top View M4A(3,5)-64 I/O7 TDI M4A(3,5)-32/32 CLK0/I0 GND TCK I/O9 A10 B2 I/O10 A11 B3 I/O11 M4A(3,5)-64/32 PIN DESIGNATIONS CLK/I ...

Page 44

TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32) Top View M4A(3,5)-64 I/O7 TDI CLK0/I0 M4A(3,5)-32/32 NC GND TCK I/O9 A10 B2 I/O10 A11 B3 I/O11 M4A(3,5)-64/32 PIN DESIGNATIONS ...

Page 45

TQFP CONNECTION DIAGRAM (M4A(3,5)-96/48) Top View NC 1 TDI I/O10 9 B3 I/O11 10 I0/CLK0 GND 13 ...

Page 46

PQFP CONNECTION DIAGRAM (M4A(3,5)-128/64) Top View GND GND TDI I5 B7 I/O8 B6 I/O9 B5 I/O10 B4 I/O11 B3 I/O12 B2 I/O13 B1 I/O14 B0 I/O15 IO/CLK0 GND GND I1/CLK1 C0 I/O16 C1 I/O17 C2 ...

Page 47

... TQFP CONNECTION DIAGRAM (M4A3-64/64 AND M4A(3,5)-128/64) Top View GND 1 TDI I/ I/ I/O10 I/O11 I/O12 7 B2 A11 I/O13 8 B1 A13 I/O14 9 B0 A15 I/O15 10 I0/CLK0 GND 13 I1/CLK1 14 I/O16 C0 B15 15 I/O17 C1 B13 16 I/O18 C2 B11 ...

Page 48

... CONNECTION DIAGRAM (M4A3-128/64) Bottom View 10 9 I/O63 GND A H7 TRST GND B I/O53 TDO C G5 I/O50 I/O55 I/O49 E CLK3/ GND VCC I/O41 CLK2/ I/O44 I/O45 I/O47 J ENABLE F7 I/O39 K GND PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI ...

Page 49

TQFP CONNECTION DIAGRAM (M4A(3,5)-192/96) Top View GND 1 TDI ...

Page 50

... FPBGA CONNECTION DIAGRAM (M4A3-192/96) Bottom View I/O72 I/O76 A GND L7 L3 I/O73 I/O77 I/O79 B GND L6 L2 I/O74 C GND TDO L5 I/O67 I/O69 I/O71 I/O75 I/O64 I/O66 I/O70 E I12 K7 K5 I/065 F I10 I11 GND I/O60 I/O61 I/O62 I/O63 ...

Page 51

... Supply Voltage = Test Data In = Test Clock = Test Mode Select Test Data Out = Test Reset I/O Cell = Program PAL Block ispMACH 4A Family M4A3-256/160 M4A(3, 5)- 256/128 156 GND GND 155 TDO TDO RECOMMEND TO TIE TO VCC 154 TRST NC 153 I/O111 N7 I/O139 N15 152 I/O110 ...

Page 52

... PQFP CONNECTION DIAGRAM (M4A3-384/160 AND M4A3-512/160) Top View GND GND 1 TDI TDI 2 F7 I/O18 C7 I/O18 3 F6 I/O19 C6 I/O19 4 F5 I/O20 C5 I/O20 5 F4 I/O21 C4 I/O21 6 F3 I/O22 C3 I/O22 7 F2 I/O23 C2 I/O23 8 F1 I/O24 C1 I/O24 9 F0 I/O25 C0 I/O25 10 VCC VCC 11 GND GND ...

Page 53

... BGA CONNECTION DIAGRAM (M4A3-256/128) Bottom View I/O108 I/O105 A GND N/C GND GND N4 N1 I/O113 I/O109 I/O106 I/O103 B GND N I/O116 I/O111 I/O107 TRST C N/C VCC I/O120 I/O117 I/O112 I/O110 D VCC VCC I/O123 I/O119 I/O114 E TDI ...

Page 54

... CONNECTION DIAGRAM (M4A3-256/192) Bottom View I/O167 I/O181 I/O180 I/O177 I/O174 A N15 O13 O12 O9 O6 I/O165 I/O166 I/O182 I/O179 I/O175 B N13 N14 O14 O11 O7 I/O163 I/O164 I/O183 I/O178 C NC N11 N12 O15 O10 I/O158 I/O159 D TDO GND GND ...

Page 55

... BGA CONNECTION DIAGRAM - (M4A3-384/192) Bottom View I/O11 I/O44 I/O58 A GND GND GND FX7 FX6 CX6 I/O12 I/O28 I/O45 I/O59 I/O64 B GND GX7 FX5 FX3 CX7 CX5 I/O0 I/O13 I/O46 I/O60 I/O65 C VCC GX5 FX4 GX6 FX2 FX1 I/O1 I/O14 ...

Page 56

... CONNECTION DIAGRAM (M4A3-256/128) Bottom View I/O117 I/O116 I/O113 I/O126 TRST I/O110 I/O111 I/O118 I/O115 I/O127 I/O108 I/O109 I/O119 I/O114 I/O104 D NC TDO GND GND N0 I/O102 I/O107 I/O105 E NC VCC ...

Page 57

... CONNECTION DIAGRAM (M4A3-384/192) Bottom View I/O175 I/O181 I/O180 I/O177 A FX7 GX5 GX4 GX1 I/O173 I/O174 I/O182 I/O179 B FX5 FX6 GX6 GX3 I/O171 I/O172 I/O183 C N/C FX3 FX4 GX7 I/O150 I/O151 D TDO GND CX6 CX7 I/O148 I/O170 E N/C VCC CX4 ...

Page 58

... CONNECTION DIAGRAM (M4A3-512/192) Bottom View I/O159 I/O181 I/O180 I/O177 I/O174 A KX7 OX5 OX4 OX1 I/O157 I/O158 I/O182 I/O179 I/O175 B KX5 KX6 OX6 OX3 I/O155 I/O156 I/O183 I/O178 C N/C KX3 KX4 OX7 OX2 I/O150 I/O151 D TDO GND GND JX6 ...

Page 59

... CONNECTION DIAGRAM (M4A3-512/256) Bottom View GND I/O243 I/O240 I/O241 I/O236 I/O231 I/O228 A OX3 OX0 OX1 NX4 MX7 MX4 GND I/O245 I/O242 I/O238 I/O234 I/O232 B N/C OX5 OX2 NX6 NX2 NX0 I/O213 GND I/O247 I/O244 I/O239 I/O235 C TDO ...

Page 60

... PRODUCT ORDERING INFORMATION ispMACH 4A Devices Commercial and Industrial - 3.3V and 5V Lattice programmable logic products are available with several ordering options. The order number (Valid Combination) is formed by a combina- tion of: FAMILY TYPE M4A3- = ispMACH 4A Family Low Voltage Advanced Feature (3.3 M4A5- = ispMACH 4A Family Advanced Feature ...

Page 61

... YC, VC M4A5-128/64 VC M4A5-192/96 YC M4A5-256/128 3.3V Industrial Combinations VNC, VNC48, JNC M4A3-32/32 VNC, VNC48, JNC M4A3-64/32 VNC M4A3-64/64 VNC M4A3-128/64 VNC M4A3-192/96 FANC, YNC M4A3-256/128 YNC M4A3-256/160 FANC M4A3-256/192 FANC M4A3-384/192 FANC M4A3-512/192 VNC, VNC48, JNC M4A5-32/32 VNC, VNC48, JNC M4A5-64/32 VNC M4A5-96/48 ...

Page 62

... September 2006 M Revised M4A3-256/160 208-pin PQFP connection diagram. © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

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