MAX1304ECM Maxim Integrated, MAX1304ECM Datasheet - Page 20

• Manufacturer Part Number: MAX1304ECM
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1304ECM

• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 1075 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Snr: 71 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-48
• Maximum Power Dissipation: 1818.2 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

The data throughput (f
MAX1308–MAX1310/MAX1312–MAX1314 is a function
of the clock speed (f
15MHz (typ). In external clock mode, 100kHz ≤ f
20MHz. When reading during conversion (Figures 7 and
8), calculate f
where N is the number of active channels and t
the period of bus inactivity before the rising edge of
CONVST. See the Starting a Conversion section for
more information.
Table 1 uses the above equation and shows the total
throughput as a function of the number of channels
selected for conversion.
Table 1. Throughput vs. Channels Sampled: f
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
20
CHANNELS
______________________________________________________________________________________
f
SAMPLED
TH
(N)
=
1
2
3
4
5
6
7
8
t
ACQ
TH
as follows:
+
t
CLK
QUIET
CLOCK CYCLES
LAST RESULT
TH
). In internal clock mode, f
) of the MAX1304–MAX1306/
UNTIL
+
12
15
18
21
24
27
30
33
12
1
+
Data Throughput
3
x N
f
CLK
(
LAST CONVERSION
−
CLOCK CYCLE
FOR READING
1
)
+
QUIET
1
1
1
1
1
1
1
1
1
CLK
CLK
is
=
≤
CLK
The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–
MAX1314 provide a 15MHz internal conversion clock.
Alternatively, an external clock can be used.
Internal clock mode frees the microprocessor from the
burden of running the ADC conversion clock. For inter-
nal clock operation, connect INTCLK/EXTCLK to AVDD
and connect CLK to DGND. Note that INTCLK/EXTCLK
is referenced to AV
For external clock operation, connect INTCLK/EXTCLK
to AGND and connect an external clock source to CLK.
Note that INTCLK/EXTCLK is referenced to AVDD, not
DVDD. The external clock frequency can be up to
20MHz. Linearity is not guaranteed with clock frequen-
cies below 100kHz due to droop in the T/H circuits.
CONVERSION
TIME (ns)
= 15MHz, t
TOTAL
1000
1200
1400
1600
1800
2000
2200
800
ACQ
DD
THROUGHPUT
, not DV
TOTAL
= 100ns, t
(ksps)
1643
2117
2474
2752
2975
3157
3310
983
DD
.
QUIET
Clock Modes
PER CHANNEL
THROUGHPUT
External Clock
Internal Clock
(f
= 50ns
983
821
705
618
550
495
451
413
TH
)