MAX1304ECM Maxim Integrated, MAX1304ECM Datasheet - Page 6

• Manufacturer Part Number: MAX1304ECM
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1304ECM

• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 1075 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Snr: 71 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-48
• Maximum Power Dissipation: 1818.2 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
ELECTRICAL CHARACTERISTICS (continued)
(V
C
lar devices), f
unless otherwise noted. Typical values are at T
6
Note 1: For the MAX1304/MAX1305/MAX1306, V
Note 2: All channel performance is guaranteed by correlation to a single channel test.
Note 3: The analog input resistance is terminated to an internal bias point (Figure 5). Calculate the analog input current using:
Note 4: Throughput rate is given per channel. Throughput rate is a function of clock frequency (f
Note 5: The REF input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF input current using:
Note 6: The REF
Note 7: All analog inputs are driven with a -0.4dBFS 500kHz sine wave.
Note 8: Shutdown current is measured with the analog input unconnected. The large amplitude of the maximum shutdown current
Note 9: CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor droop.
Note 10: CS to WR and CS to RD are internally AND together. Setup and hold times do not apply.
Note 11: Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CONVST
Input-Data Setup Time
Input-Data Hold Time
External CLK Period
External CLK High Period
External CLK Low Period
External Clock Frequency
Internal Clock Frequency
CONVST High to CLK Edge
REF-
AVDD
_______________________________________________________________________________________
= 0.1µF, C
= +5V, V
I
MAX1312/MAX1313/MAX1314, V
for V
put rate is specified with f
Data Throughput section for more information.
I
for V
for V
specification is due to automated test equipment limitations.
and the falling edge of EOLC to a maximum of 1ms.
I
CH
REF
REFMS
PARAMETER
_
CLK
CH_
REF
REFMS
=
=
DVDD
V
REF+-to-REF-
V
=
MS
REF
within the input voltage range.
CH
within the input voltage range.
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T
V
R
REFMS
R
input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF
within the input voltage range.
_
REF
− 2 5 .
= +3V, V
CH
R
−
REFMS
V
_
BIAS
V
− 2 5 .
= 2.2µF || 0.1µF, C
AGND
V
CLK
= V
= 16.67MHz and the internal clock throughput rate is specified with f
SYMBOL
DGND
t
t
t
t
t
CLKH
CNTC
t
CLKL
f
IN
f
DTW
WTD
CLK
CLK
INT
= -10V to +10V.
A
= 0V, V
COM
= +25°C. See Figures 3 and 4.)
IN
Figure 6
Figure 6
Figures 8, 9
Logic sensitive to rising edges,
Figures 8, 9
Logic sensitive to rising edges,
Figures 8, 9
(Note 11)
Figures 8, 9
= 0 to +5V. For the MAX1308/MAX1309/MAX1310, V
= 2.2µF || 0.1µF, C
REF
= V
REFMS
CONDITIONS
= +2.5V (external reference), C
MSV
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
0.05
MIN
CLK
0.1
10
10
20
20
20
REF
). The external clock through-
= C
IN
TYP
MS
= -5V to +5V. For the
15
CLK
REFMS
input current using:
= 15MHz. See the
A
= 0.1µF, C
10.00
= T
MAX
20
MIN
to T
UNITS
MHz
MHz
REF+
ns
ns
µs
ns
ns
ns
MAX
=
,