W7100A WIZnet, W7100A Datasheet - Page 103

• Manufacturer Part Number: W7100A
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 255 B
• Data Ram Size: 64 KB
• On-chip Adc: No
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 80 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• Interface Type: UART
• Program Memory Type: Flash

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100n)][0x0000]
of SOCKET n. The host can’t write data as a size bigger than Sn_TX_FSR. Therefore, be sure to
check Sn_TX_FSR before transmitting data, and if your data size is smaller than or the same
as Sn_TX_FSR, transmit the data with SEND or SEND_MAC command after copying the data.
received from the peer), Sn_TX_FSR is automatically increased by the size of that transmitted
DATA packet. At the other modes, when Sn_IR(SENDOK) is ‘1’, Sn_TX_FSR is automatically
increased by the size of the transmitted data.
0x100n)][0x0000]
SEND command of SOCKET n Command Register, it transmits data from the current Sn_TX_RD
to the Sn_TX_WR and automatically updates after transmission is finished. Therefore, after
transmission is finished, Sn_TX_RD and Sn_TX_WR will have the same value. When reading this
register, the user should read the upper bytes (0xFE4022, 0xFE4122, 0xFE4222, 0xFE4322,
0xFE4422, 0xFE4522, 0xFE4622, 0xFE4722) first and lower bytes (0xFE4023, 0xFE4123,
0xFE4223, 0xFE4323, 0xFE4423, 0xFE4523, 0xFE4623, 0xFE4723) later to get the correct value.
+ 0x100n)][0x0000]
written. When reading this register, the user should read the upper bytes (0xFE4024,
0xFE4124, 0xFE4224, 0xFE4324, 0xFE4424, 0xFE4524, 0xFE4624, 0xFE4724) first and the lower
bytes (0xFE4025, 0xFE4125, 0xFE4225, 0xFE4325, 0xFE4425, 0xFE4525, 0xFE4625, 0xFE4725)
later to get the correct value.
Sn_TX_FSR (SOCKET n TX Free Size Register)[R][(0xFE4020 + 0x100n) – (0xFE4021 +
It notifies the available size of the internal TX memory (the byte size of transmittable data)
At the TCP mode, if the peer checks the transmitted DATA packet (if DATA/ACK packet is
Sn_TX_RD (SOCKET n TX Read Pointer Register)[R][(0xFE4022 + 0x100n) – (0xFE4023 +
This register shows the address of the last transmission finishing in the TX memory. With the
Sn_TX_WR (SOCKET n TX Write Pointer Register)[R/W][(0xFE4024 + 0x100n) – (0xFE4025
This register offers the location information of where the transmission data should be
Ex8) SOCKET 6 : 2KB, SOCKET 7 : 2KB
As shown above ex5) ~ ex8), total size of each SOCKET’s TX memory (Sn_TXMEM_S
IZE
Ex) In case of 2048(0x8000) in S0_TX_FSR0
SUM
) is 16Kbytes.
0xFE461F
0xFE4020
0x02
0x08
0xFE471F
0xFE4021
0x02
0x00
Ver. 1.12
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