W7100A WIZnet, W7100A Datasheet - Page 11

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W7100A

Manufacturer Part Number
W7100A
Description
8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
Manufacturer
WIZnet
Datasheet

Specifications of W7100A

Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
255 B
Data Ram Size
64 KB
On-chip Adc
No
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 80 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
Interface Type
UART
Program Memory Type
Flash

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© Copyright 2011 WIZnet Co., Inc. All rights reserved.
1
1.1
64KB SRAM and hardwired TCP/IP Core for high performance and easy development.
MAC & PHY. The Hardwired TCP/IP stack supports the TCP, UDP, IPv4, ICMP, ARP, IGMP and
PPPoE which has been used in various applications for years.
1.2
iMCU W7100A is the one-chip solution which integrates an 8051 compatible microcontroller,
The TCP/IP core is a market-proven hardwired TCP/IP stack with an integrated Ethernet
Pipelined architecture which enables execution of instructions 4~5 times faster than a
10BaseT/100BaseTX Ethernet PHY embedded
Power down mode supported for saving power consumption
Hardwired TCP/IP Protocols: TCP, UDP, ICMP, IPv4 ARP, IGMP, PPPoE, Ethernet
Auto Negotiation (Full-duplex and half duplex), Auto MDI/MDIX
ADSL connection with PPPoE Protocol with PAP/CHAP Authentication mode support
8 independent sockets which are running simultaneously
32Kbytes Data buffer for the Network
Network status LED outputs (TX, RX, Full/Half duplex, Collision, Link, and Speed)
Not supports IP fragmentation
2 Data Pointers (DPTRs) for fast memory blocks processing
64KBytes Data Memory (RAM)
Up to 16M bytes of external (off-chip) data memory
Interrupt controller
Four 8-bit I/O Ports
Three timers/counters
Full-duplex UART
Programmable Watchdog Timer
DoCD™ compatible debugger
Fully software compatible with industrial standard 8051
standard 8051
255Bytes data FLASH, 64KBytes Code Memory, 2KBytes Boot Code Memory
Advanced INC & DEC modes
Auto-switch of current DPTR
2 priority levels
4 external interrupt sources
1 Watchdog interrupt
Overview
Introduction
W7100A Features
Ver. 1.12
11

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