W7100A WIZnet, W7100A Datasheet - Page 151
W7100A
Manufacturer Part Number
W7100A
Description
8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
Manufacturer
WIZnet
Datasheet
1.W7100A.pdf
(156 pages)
Specifications of W7100A
Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
255 B
Data Ram Size
64 KB
On-chip Adc
No
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 80 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
Interface Type
UART
Program Memory Type
Flash
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13.3.2 Subtraction
registers pair RaRb. The second operand is located in registers pair RxRy.
13.3.3 Multiplication
in registers pair RaRb. The second operand is located in registers pair RxRy.
ADDC
SUBB
SUBB
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ADD
CLR
RaRb = RaRb + RxRy
The following code performs 16-bit subtraction. The first operand and result are located in
RaRb = RaRb – RxRy
The following code performs 16-bit multiplication. The first operand and result are located
RaRb = RaRb * RxRy
Mnemonic
Mnemonic
Mnemonic
A, Rb
A, Ry
Rb, A
A, Ra
A, Rx
A, Rb
A, Ry
Rb, A
A, Ra
A, Rx
A, Rb
Ra, A
Ra, A
C
Sum :
Sum :
E8h – EFh
28h – 2Fh
F8h – FFh
E8h – EFh
38h – 3Fh
F8h – FFh
E8h – EFh
98h – 9Fh
F8h – FFh
E8h – EFh
98h – 9Fh
F8h – FFh
E8h – EFh
Opcode
Opcode
Opcode
C3h
Byte
Byte
Byte
1
1
1
1
1
1
1
1
1
1
1
1
1
1
80C51 Cycle
80C51 Cycle
80C51 Cycle
12
12
12
12
12
12
72
12
12
12
12
12
12
12
84
12
wizmemcpy
wizmemcpy
wizmemcpy
ISP /
ISP /
ISP /
1
1
1
1
1
1
6
1
1
1
1
1
1
1
7
1
W7100A Cycle
W7100A Cycle
W7100A Cycle
Ver. 1.12
user code
user code
user code
FLASH /
FLASH /
FLASH /
24
28
4
4
4
4
4
4
4
4
4
4
4
4
4
4
151