W7100A WIZnet, W7100A Datasheet - Page 26

• Manufacturer Part Number: W7100A
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 255 B
• Data Ram Size: 64 KB
• On-chip Adc: No
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 80 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• Interface Type: UART
• Program Memory Type: Flash

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The W7100A’s memory is divided into two types of memories: “Code Memory” and “Data
Memory”. Each memory can use the memory lock function. If the lock is set, internal memory
accessing from outside is denied and also cannot use the W7100A debugger. For more detailed
information about the memory lock function, please refer to the “WizISP Program Guide”.
The memory structure of W7100A is roughly shown figure 2.1.
2.1
to 0xFFFF. After the system is reset, the W7100A always executes the code of Boot ROM at
“Code Memory.” According to the BOOTEN pin, the code of Boot ROM executes differently.
Figure 2.2 shows the flow of Boot ROM code. After the booting, the system proceeds to either
the ISP process or the APP Entry according to the BOOTEN pin. When ISP process is selected
(BOOTEN = ‘1’), the ISP code of the Boot ROM will run. Otherwise ( BOOTEN = ‘0’), the system
jumps to the APP Entry without running the ISP code of Boot ROM.
Entry is used for running user application code. The APP Entry contains the ‘memory map
switching code’ and the jumping code which jumps to the start address 0x0000 of the user
application in Code FLASH memory. The memory map switching is as below.
“Code Memory” consists the Boot ROM from 0x0000 to 0x07FF and Code FLASH from 0x0000
ISP code is used for WizISP program when writing user code to code FLASH. And the APP
Memory
Code Memory
Figure 2.1 Code / Data Memory Connections
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