W7100A WIZnet, W7100A Datasheet - Page 31

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W7100A

Manufacturer Part Number
W7100A
Description
8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
Manufacturer
WIZnet
Datasheet

Specifications of W7100A

Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
255 B
Data Ram Size
64 KB
On-chip Adc
No
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 80 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
Interface Type
UART
Program Memory Type
Flash

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signal to classify the address and data signal. User can configure the duration of ALE signal
using the ALECON(0x9F) SFR. For more detailed information about ALECON, please refer to
the section 2.5.10 ‘New & Extended SFR’.
2.3.2 Direct Interface
to “101”, the port0 is used as data line (D[7:0]) and the port1 is lower side address (A[7:0])
and the port2 is used as upper side address (A[15:8]). The remained port3 can be used as
GPIO. Using this method, user can connect data line to address line without latch. It is shown
the figure 2.8 as below.
previous case and the port3 is used as topside address (A[23:16]). In this method, there is no
port to use GPIO. It is shown the figure below.
In the Standard 8051 External pin access mode, MCU controls the ALE (Address Latch Enable)
This method is directly connecting the data line to address line. When user sets the EM[2:0]
When user sets the EM[2:0] to “111”, the port0, port1 and port2 has same usage in the
Figure 2.9 Direct 8051 External Pin Access Mode (EM[2:0] = “111”)
Figure 2.8 Direct 8051 External Pin Access Mode (EM[2:0] = “101”)
EM[2:0]=101
WCONF
(0xFF)
W7100A
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:0]
A[7:0]
A[15:8]
D[7:0]
GPIO
A[15:0]
External
Device
Ver. 1.12
31

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