W7100A WIZnet, W7100A Datasheet - Page 36

• Manufacturer Part Number: W7100A
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 255 B
• Data Ram Size: 64 KB
• On-chip Adc: No
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 80 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• Interface Type: UART
• Program Memory Type: Flash

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Note: TSL - Toggle select enable. When TSL is set, this bit toggles the SEL bit by exec
2.5.5 Clock Control Register
the dedicated data memory read/write signal pulses width.
purpose of MD[2:0] is to adjust the communication speed with I/O devices such as slow RAM,
Clock control register CKCON (0x8E) contains MD [2:0] bits which provide the information for
The dedicated data memory read/write signals are activated during MOVX instruction. The
WD1
ID1
Selected data pointer register is used in the following instructions:
MOVX @DPTR, A
MOVX A, @DPTR
MOVC A, @A + DPTR
JMP @A + DPTR
INC DPTR
MOV DPTR, #data16
7
7
uting the following instructions.
INC DPTR
MOV DPTR, #data16
MOVC A, @A + DPTR
MOVX @DPTR, A
MOVX A, @DPTR
When TSL = 0, DPTR related instructions will not affect the state of the SEL
Unimplemented bit - Read as 0 or 1.
bit.
WD0
ID0
ID1
6
6
0
0
1
1
Figure 2.23 Clock Control Register – STRETCH bits
ID0
TSL
0
1
0
1
Figure 2.22 Data Pointer Select Register
5
5
-
Table 2.3 DPTR0, DPTR1 Operations
4
-
4
-
DEC DPTR
DEC DPTR
CKCON (0x8E)
INC DPTR
INC DPTR
SEL = 0
DPS (0x86)
3
-
3
-
MD2
2
2
-
MD1
1
1
-
DEC DPTR1
DEC DPTR1
INC DPTR1
INC DPTR1
SEL = 1
MD0
SEL
Ver. 1.12
0
0
Reset
Reset
0x00
0x07
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