W7100A WIZnet, W7100A Datasheet - Page 45

• Manufacturer Part Number: W7100A
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 255 B
• Data Ram Size: 64 KB
• On-chip Adc: No
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 80 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• Interface Type: UART
• Program Memory Type: Flash

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
SM0
7
7
-
-
7
Note: RI - UART receiver interrupt flag
Note: EINT2 - Enable external INT2 Interrupt
Note: PINT2 - INT2 priority level control (high level at 1)
SM1
TI - UART transmitter interrupt flag
IE1 – INT1 interrupt flag is automatically cleared when processor branches to
TF0 - Timer0 interrupt (overflow) flag. Automatically cleared when processor
TF1 – Timer 1 interrupt (overflow) flag. Automatically cleared when processor
6
EINT3 - Enable external INT3 Interrupt
EINT4 – Must be ‘0’, if use the EIE register
EINT5 - Enable TCPIPCore Interrupt
EWDI - Enable WATCHDOG Interrupt
6
PINT3 - INT3 priority level control (high level at 1)
PINT4 – Must be set to ‘0’, if use the EIP register
PINT5 - TCPIPCore Interrupt priority level control (high level at 1)
PWDI - WATCHDOG priority level control (high level at 1)
-
-
6
interrupt routine
interrupt routine
branches to interrupt routine
branches to interrupt routine
Figure 3.6 Extended Interrupt Priority Register
Figure 3.5 Extended Interrupt Enable Register
SM2
5
5
-
-
5
Figure 3.4 UART Configuration Register
PWDI
EWDI
4
REN
4
4
SCON (0x98)
EIE (0xE8)
EIP (0xF8)
EINT5
PINT5
TB8
3
3
3
PINT4
EINT4
RB8
2
2
2
EINT3
PINT3
1
1
TI
1
EINT2
PINT2
Ver. 1.12
RI
0
0
0
Reset
Reset
Reset
0x00
0x00
0x00
45