W7100A WIZnet, W7100A Datasheet - Page 50

• Manufacturer Part Number: W7100A
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 255 B
• Data Ram Size: 64 KB
• On-chip Adc: No
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 80 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• Interface Type: UART
• Program Memory Type: Flash

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
5
the timer registers are incremented by every 12 CLK periods. In “counter mode”, the timer
registers are incremented during the falling transition on their corresponding input pins: T0 or
T1. The input pins are sampled at every CLK period.
5.1
5.1.1 Overview
unidirectional. There are no tri-state output pins and internal signals.
Pin
T0/FCS
GATE0/FOE
T1/FAE
GATE1/FA0
of two 8-bit registers, TH0 (0x8C) and TL0 (0x8A), TH1 (0x8D) and TL1 (0x8B). The timers
work in four modes which are described below.
The W7100A contains two 16-bit timers/counters, Timer0 and Timer 1. In the ‘timer mode’,
The Timer0, 1 pin functionalities are described in the following table. All pins are
Timer0 and Timer 1 are fully compatible with the standard 8051 timers. Each timer consists
M1
0
0
1
1
Timers
Timers 0, 1
M0
0
1
0
1
Active
Falling
High
Falling
High
Mode
0
1
2
3
Function Description
THx operates as a 8-bit timer/counter with a divided-by-32
prescaler served by lower 5-bit of TLx
16-bit timer/counter. THx and TLx are cascaded.
TLx operates as a 8-bit timer/counter with 8bit auto-reload by
THx.
TL0 is configured as a 8-bit timer/counter controlled by the
standard Timer0 bits. TH0 is a 8-bit timer controlled by Timer 1
control bits. Timer 1 holds its count.
Type
I
I
I
I
Table 5.1 Timers 0, 1 Pin Description
Table 5.2 Timers 0, 1 Mode
Pu/Pd
-
-
-
-
Description
Timer0 clock
Timer0 clock
Timer1 clock
Timer1 clock
gate control
gate control
Ver. 1.12
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