W7100A WIZnet, W7100A Datasheet - Page 61

no-image

W7100A

Manufacturer Part Number
W7100A
Description
8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
Manufacturer
WIZnet
Datasheet

Specifications of W7100A

Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
255 B
Data Ram Size
64 KB
On-chip Adc
No
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 80 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
Interface Type
UART
Program Memory Type
Flash

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W7100A
Manufacturer:
WIZNET
Quantity:
9 870
Part Number:
W7100A
Manufacturer:
IDT
Quantity:
3
Part Number:
W7100A
Manufacturer:
WIZNET
Quantity:
103
Part Number:
W7100A
Manufacturer:
WIZNET
Quantity:
20 000
Part Number:
W7100A-100LQFP
Manufacturer:
POWEREX
Quantity:
1 000
Part Number:
W7100A-64QFN
Manufacturer:
WIZNET
Quantity:
1 400
© Copyright 2011 WIZnet Co., Inc. All rights reserved.
6
transmitting at the same time. Since the W7100A is double-buffered, the receiver is capable
of receiving data while the first byte of the buffer is not read. During a read operation, the
SBUF reads from the receive register. On the other hand, SBUF loads the data into the
transmit register during a send operation. The UART has 4 different modes which include one
in synchronous mode and three in asynchronous modes. Modes 2 and 3 include a special
feature for multiprocessor communication. This feature is enabled by setting the SM2 bit in
the SCON register. The master processor sends out the first address byte which identifies the
target slave. An address byte differs from a data byte in that the 9
and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte, while an
address byte will interrupt all slaves. The addressed slave will clear its SM2 bit and prepare to
receive the data bytes that will be coming. The slaves that were not being addressed leave
their SM2 set and ignore the incoming data.
Pin
RXD
TXD
registers are: SBUF (0x99), SCON (0x98), PCON (0x87), IE (0xA8) and IP (0xB8). The UART data
buffer (SBUF) consists of two registers: transmit and receive. When data is written into the
SBUF transmit register, the sending process begins. Similarly, data is read from the receive
register during the receiving process.
The UART of W7100A operates in full duplex mode which is capable of receiving and
The pin functionalities of UART are described in the following table.
The UART of W7100A is fully compatible with the standard 8051 UART. The UART related
SM0
SB7
Active
7
7
Note:
UART
-
-
SB6
SM1
SM2 - Enable a multiprocessor communication feature
SM1 - Set baud rate
SM0 - Set baud rate
Type
6
6
O
I
SB5
SM2
5
5
Figure 6.2 UART Configuration Register
Pu/Pd
Pu
-
Figure 6.1 UART Buffer Register
Table 6.1 UART Pin Description
SB4
REN
4
4
Description
Serial receiver input / output
Serial transmitter
SCON (0x98)
SBUF (0x99)
SB3
TB8
3
3
SB2
RB8
2
2
SB1
TI
1
th
1
bit is 1 in an address byte
SB0
Ver. 1.12
RI
0
0
Reset
Reset
0x00
0x00
61

Related parts for W7100A