W7100A WIZnet, W7100A Datasheet - Page 63

• Manufacturer Part Number: W7100A
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 255 B
• Data Ram Size: 64 KB
• On-chip Adc: No
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 80 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• Interface Type: UART
• Program Memory Type: Flash

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result by hardware. That is, interrupts can be generated or cancelled by software.
6.2
bits are transmitted with LSB first. Reception is initialized by setting the flags in SCON as
follows: RI = 0 and REN = 1.
All of the bits that generate interrupts can be set or cleared by software, with the same
TXD output is a shift clock. The baud rate is fixed at 1/12 of the CLK clock frequency. Eight
Interrupt
SM0
TI & RI
EA
7
7
7
Flag
-
Note: ES - RI & TI interrupt enable flag
Note: SMOD0 - Bit for UART baud rate
Note: TI – Transmit interrupt flag, automatically set after completion of a serial
Mode0, Synchronous
Unimplemented bit - Read as 0 or 1
SM1
RI – Receive interrupt flag, automatically set after completion of a serial
6
6
6
-
-
Internal, UART
Function
reception. It must be cleared by software.
Figure 6.5 UART Bits in Interrupt Priority Register
Figure 6.4 UART Bits in Interrupt Enable Register
transfer. It must be cleared by software.
SM2
ET2
PT2
5
Figure 6.6 UART Configuration Register
5
5
Table 6.4 UART Interrupt
REN
Level/Edge
ES
PS
4
4
4
Active
-
SCON (0x98)
TB08
IE (0xA8)
IP (0xB8)
PT1
ET1
3
3
3
Flag Resets
software
RB08
EX1
PX1
2
2
2
Vector
ET0
PT0
0x23
TI
1
1
1
Natural Priority
Ver. 1.12
PX0
EX0
RI
0
0
0
5
Reset
Reset
Reset
0x00
0x00
0x00
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