W7100A WIZnet, W7100A Datasheet - Page 69

• Manufacturer Part Number: W7100A
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 255 B
• Data Ram Size: 64 KB
• On-chip Adc: No
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 80 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• Interface Type: UART
• Program Memory Type: Flash

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
7.7
has to be performed using ‘7.8 Timed Access Registers’ procedure.
The table below summarizes Watchdog control bits and the functions.
EWT
Watchdog control bits are described below. Please note that access (write) to this register
X
0
0
1
1
7
-
Note: WTRF - Watchdog Timer reset Flag. A Watchdog Timer reset has occurred
Watchdog Control
EWDI
X
0
1
0
1
6
RWT – Reset the Watchdog Timer. Setting RWT resets the Watchdog Timer
Unimplemented bit - Read as 0 or 1
-
EWT – Enable the Watchdog Timer reset. This bit controls the Watchdog
WDIF
0
1
1
1
1
when this flag is enabled; however, when using software to enable
et, this flag is cleared otherwise it should be cleared by software.
ed.
ity of the Watchdog Timer to generate a Watchdog interrupt. Tim
ed Access procedure must be used to modify this bit.
bit before the Watchdog Timer expires, reset or interrupt will be
generated if the RWT is enabled.
this flag, the Watchdog timer reset is not triggered. During a res
The Watchdog Timer has no effect on this bit if EWT bit is clear
Timer to reset the microcontroller, and has no effect on the abil
count. Timed Access procedure must be followed to enable this
0 : Watchdog Timer timeout does not reset microcontroller
1 : Watchdog Timer timeout resets microcontroller
5
-
Figure 7.6 Watchdog Control Register
Result
No Watchdog event.
Watchdog timeout has expired. No interrupt has been generated.
Watchdog interrupt has occurred.
Watchdog timeout has expired. No interrupt has been generated.
Watchdog Timer reset will occur in 512 clock periods (CLK pin) if
RWT is not strobed.
occur in 512 clock periods (CLK pin) if RWT is not set using Timed
Access procedure.
Table 7.3 Watchdog Bits and Actions
Watchdog interrupt has occurred. Watchdog Timer reset will
4
-
WDCON (0xD8)
WDIF
3
WTRF
2
EWT
1
RWT
Ver. 1.12
0
Reset
0x00
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