W7100A WIZnet, W7100A Datasheet - Page 88

no-image

W7100A

Manufacturer Part Number
W7100A
Description
8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
Manufacturer
WIZnet
Datasheet

Specifications of W7100A

Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
255 B
Data Ram Size
64 KB
On-chip Adc
No
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 80 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
Interface Type
UART
Program Memory Type
Flash

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W7100A
Manufacturer:
WIZNET
Quantity:
9 870
Part Number:
W7100A
Manufacturer:
IDT
Quantity:
3
Part Number:
W7100A
Manufacturer:
WIZNET
Quantity:
103
Part Number:
W7100A
Manufacturer:
WIZNET
Quantity:
20 000
Part Number:
W7100A-100LQFP
Manufacturer:
POWEREX
Quantity:
1 000
Part Number:
W7100A-64QFN
Manufacturer:
WIZNET
Quantity:
1 400
© Copyright 2011 WIZnet Co., Inc. All rights reserved.
W7100A supports two types of Authentication method - PAP and CHAP.
information, please refer to PPPoE application note.
application note of W5100, “How to connect ADSL”.
signal Low Assert waiting time until next interrupt. If user wants to use TCP/IP Core interrupt,
INTLEVEL register must be set higher than 0x2B00.
ignored.
TCP
PATR (Authentication Type in PPPoE mode) [R] [0xFE001C-0xFE001D] [0x0000]
This register notifies the type of authentication used to establish the PPPoE connection.
PPPALGO (Authentication Algorithm in PPPoE mode)[R][0xFE001E][0x00]
This register notifies the authentication algorithm used for the PPPoE connection. For detail
PTIMER (PPP Link Control Protocol Request Timer Register) [R/W] [0xFE0028] [0x28]
This register indicates the duration of LCP Echo Request being sent. Value 1 is about 25ms.
PMAGIC (PPP Link Control Protocol Magic number Register) [R/W] [0xFE0029][0x00]
This register is used in the Magic number option during LCP negotiation. Refer to the
VERSIONR (W7100A Chip Version Register)[R][0xFE001F][0x02]
This register is W7100A chip version register.
INTLEVEL (Interrupt Low Level Timer Register)[R/W][0xFE0030 – 0xFE0031][0x0000]
The INTLEVEL register sets the Interrupt Assert wait time(I
TO
Ex) in case that PTIMER is 200,
= (2000 + 4000 + 8000 + 16000 + 32000 + ((8 - 4) X 64000)) X 0.1ms
= 318000 X 0.1ms = 31.8s
= (0x07D0 + 0x0FA0 + 0x1F40 + 0x3E80 + 0x7D00 + 0xFA00 + 0xFA00 + 0xFA00 + 0xFA00) X 0.1ms
200 * 25(ms) = 5000(ms) = 5 seconds
0xC023
0xC223
Value
I
AWT
= (INTLEVEL0 + 1) * PLL_CLK (when INTLEVEL0 > 0)
Authentication Type
CHAP
PAP
Or the TCP/IP Core interrupt can be
AWT
). It configures internal INT5
Ver. 1.12
88

Related parts for W7100A